Publication: Towards ultra-low power consumption VAD architectures with mixed signal circuits
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2023
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IEEE
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Abstract
A voice activity detector architecture based on an analog feature extractor and a mixed signal classification stage is proposed for ultra-low power activity. The feature extraction stage is composed of a set of analog band-pass filters and frame energy estimators. The classification stage has a fully connected first layer built with ultra-low power consumption ring oscillators, followed by gated recurrent unit layers. The ring oscillator based layer consumes nWs according to transient simulations performed in a low power 65 nm CMOS technology. Additionally it features the ability to perform the analog-to-digital conversion required to handle subsequent GRU layers, as well as the possibility of computing a non-linear function like sigmoid seizing the intrinsic non-linearity of the ring oscillator. Training and testing operations are made proving competitive classification performance between a baseline model and our proposed architecture. In light of this, proper features for deployment on power-restricted edge-computing applications are shown.
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Proceedings of: 56th Edition IEEE ISCAS 2023 - IEEE International Symposium on Circuits and Systems (ISCAS), 21-25 May 2023, Monterey, CA, USA.
Keywords
Voice activity detection (VAD), Analog feature extraction, Recurrent neural network (RNN), Gated recurrent unit (GRU), Ring oscillator (RO)
Bibliographic citation
Shen, Y., Straeussnigg, D. & Gutierrez, E. (21-25 May 2023). Towards Ultra-Low Power Consumption VAD Architectures with Mixed Signal Circuits [proceedings]. 56th Edition IEEE ISCAS 2023: IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA.