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Towards ultra-low power consumption VAD architectures with mixed signal circuits

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dc.affiliation.dptoUC3M. Departamento de Tecnología Electrónicaes
dc.affiliation.grupoinvUC3M. Grupo de Investigación: Diseño Microelectrónico y Aplicaciones (DMA)es
dc.contributor.authorShen, Yukai
dc.contributor.authorStraeussnigg, Dietmar
dc.contributor.authorGutiérrez Fernández, Eric
dc.contributor.funderEuropean Commissionen
dc.date.accessioned2023-08-22T07:15:14Z
dc.date.available2023-08-22T07:15:14Z
dc.date.issued2023
dc.descriptionProceedings of: 56th Edition IEEE ISCAS 2023 - IEEE International Symposium on Circuits and Systems (ISCAS), 21-25 May 2023, Monterey, CA, USA.en
dc.description.abstractA voice activity detector architecture based on an analog feature extractor and a mixed signal classification stage is proposed for ultra-low power activity. The feature extraction stage is composed of a set of analog band-pass filters and frame energy estimators. The classification stage has a fully connected first layer built with ultra-low power consumption ring oscillators, followed by gated recurrent unit layers. The ring oscillator based layer consumes nWs according to transient simulations performed in a low power 65 nm CMOS technology. Additionally it features the ability to perform the analog-to-digital conversion required to handle subsequent GRU layers, as well as the possibility of computing a non-linear function like sigmoid seizing the intrinsic non-linearity of the ring oscillator. Training and testing operations are made proving competitive classification performance between a baseline model and our proposed architecture. In light of this, proper features for deployment on power-restricted edge-computing applications are shown.en
dc.description.sponsorshipThis paper was supported by program H2020-MSCA-ITN-2020 grant Nr.956601.en
dc.format.extent5
dc.identifier.bibliographicCitationShen, Y., Straeussnigg, D. & Gutierrez, E. (21-25 May 2023). Towards Ultra-Low Power Consumption VAD Architectures with Mixed Signal Circuits [proceedings]. 56th Edition IEEE ISCAS 2023: IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA.en
dc.identifier.doihttps://doi.org/10.1109/ISCAS46773.2023.10181669
dc.identifier.issn2158-1525
dc.identifier.publicationfirstpage1
dc.identifier.publicationlastpage5
dc.identifier.publicationtitleProceedings of 2023 IEEE International Symposium on Circuits and Systems (ISCAS)en
dc.identifier.urihttps://hdl.handle.net/10016/38065
dc.identifier.uxxiCC/0000034125
dc.language.isoeng
dc.publisherIEEE
dc.relation.eventdate2023-05-21
dc.relation.eventplaceESTADOS UNIDOS DE AMERICAes
dc.relation.eventtitle56th Edition IEEE ISCAS 2023: IEEE International Symposium on Circuits and Systems (ISCAS)en
dc.relation.projectIDinfo:eu-repo/grantAgreement/EC/956601
dc.rights© 2023 IEEE.es
dc.rights.accessRightsopen accessen
dc.subject.ecienciaEducaciónes
dc.subject.ecienciaElectrónicaes
dc.subject.ecienciaTelecomunicacioneses
dc.subject.otherVoice activity detection (VAD)en
dc.subject.otherAnalog feature extractionen
dc.subject.otherRecurrent neural network (RNN)en
dc.subject.otherGated recurrent unit (GRU)en
dc.subject.otherRing oscillator (RO)en
dc.titleTowards ultra-low power consumption VAD architectures with mixed signal circuitsen
dc.typeconference proceedings*
dc.type.hasVersionAM*
dspace.entity.typePublication
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