RT Conference Proceedings
T1 Towards ultra-low power consumption VAD architectures with mixed signal circuits
A1 Shen, Yukai
A1 Straeussnigg, Dietmar
A1 Gutiérrez Fernández, Eric
AB A voice activity detector architecture based on an analog feature extractor and a mixed signal classification stage is proposed for ultra-low power activity. The feature extraction stage is composed of a set of analog band-pass filters and frame energy estimators. The classification stage has a fully connected first layer built with ultra-low power consumption ring oscillators, followed by gated recurrent unit layers. The ring oscillator based layer consumes nWs according to transient simulations performed in a low power 65 nm CMOS technology. Additionally it features the ability to perform the analog-to-digital conversion required to handle subsequent GRU layers, as well as the possibility of computing a non-linear function like sigmoid seizing the intrinsic non-linearity of the ring oscillator. Training and testing operations are made proving competitive classification performance between a baseline model and our proposed architecture. In light of this, proper features for deployment on power-restricted edge-computing applications are shown.
PB IEEE
SN 2158-1525
YR 2023
FD 2023
LK https://hdl.handle.net/10016/38065
UL https://hdl.handle.net/10016/38065
LA eng
NO Proceedings of: 56th Edition IEEE ISCAS 2023 - IEEE International Symposium on Circuits and Systems (ISCAS), 21-25 May 2023, Monterey, CA, USA.
NO This paper was supported by program H2020-MSCA-ITN-2020 grant Nr.956601.
DS e-Archivo
RD 1 jul. 2024