Publication:
Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection

Simple item page
dc.affiliation.dptoUC3M. Departamento de Tecnología Electrónicaes
dc.affiliation.grupoinvUC3M. Grupo de Investigación: Diseño Microelectrónico y Aplicaciones (DMA)es
dc.contributor.authorPeña Fernandez, Manuel
dc.contributor.authorSerrano-Cases, A.
dc.contributor.authorLindoso Muñoz, Almudena
dc.contributor.authorGarcía Valderas, Mario
dc.contributor.authorEntrena Arrontes, Luis Alfonso
dc.contributor.authorMartinez-Alvarez, A.
dc.contributor.authorCuenca-Asensi, S.
dc.contributor.funderMinisterio de Economía y Competitividad (España)es
dc.contributor.funderComunidad de Madrides
dc.date.accessioned2021-05-20T09:18:50Z
dc.date.available2021-09-01T23:00:04Z
dc.date.issued2019-09
dc.description.abstractThis work presents a new Dual-Core LockStep approach to enhance fault tolerance in microprocessors. The proposed technique is based on the combination of software-based data checking and trace-based control-flow checking through an external hardware module. The hardware module is connected to the trace interface and is able to observe the execution of all the processors in the architecture. The proposed approach has been implemented for a dual core commercial processor. Experimental results demonstrate that the proposed technique has a high error detection capability with up to 99.63% error coverage.en
dc.format.extent5
dc.identifier.bibliographicCitationPeña-Fernández, M., Serrano-Cases, A., Lindoso, A., García-Valderas, M., Entrena, L., Martínez-Álvarez, A. & Cuenca-Asensi, S. (2019). Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection. Microelectronics Reliability, vol. 100-101, 113447.en
dc.identifier.doihttps://doi.org/10.1016/j.microrel.2019.113447
dc.identifier.issn0026-2714
dc.identifier.publicationfirstpage113447
dc.identifier.publicationtitleMicroelectronics Reliabilityen
dc.identifier.publicationvolume100-101
dc.identifier.urihttps://hdl.handle.net/10016/32696
dc.identifier.uxxiAR/0000024612
dc.language.isoeng
dc.publisherElsevieren
dc.relation.projectIDGobierno de España. ESP2015-68245-C4-1-Pes
dc.relation.projectIDComunidad de Madrid. IND2017/TIC-7776es
dc.relation.projectIDGobierno de España. ESP2015-68245-C4-3-Pes
dc.rights© 2019 Elsevier Ltd.en
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 Españaes
dc.rights.accessRightsopen access
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.subject.ecienciaElectrónicaes
dc.titleDual-Core Lockstep enhanced with redundant multithread support and control-flow error detectionen
dc.typeresearch article*
dc.type.hasVersionAM*
dspace.entity.typePublication
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
Dual-Core_MR_2019_ps.pdf
Size:
791.38 KB
Format:
Adobe Portable Document Format
Download
Collections
DTE - DMA - Artículos de Revistas