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  • Publication
    Challenging the security of "A PUF-based hardware mutual authentication protocol"
    (Elsevier, 2022-11) Adeli, Morteza; Bagheri, Nasour; Martín González, Honorio; Peris López, Pedro; Comunidad de Madrid; Ministerio de Economía y Competitividad (España)
    Recently, using Physical Unclonable Functions (PUF) to design lightweight authentication protocols for constrained environments such as the Internet of Things (IoT) has received much attention. In this direction, Barbareschi et al. recently proposed PHEMAP in Journal of Parallel and Distributed Computing, a PUF based mutual authentication protocol. Also, they extended it to the later designed Salted PHEMAP, for low-cost cloud-edge (CE) IoT devices. This paper presents the first third-party security analysis of PHEMAP and Salted PHEMAP to the best of our knowledge. Despite the designer's claim, we show that these protocols are vulnerable to impersonation, de-synchronization, and traceability attacks. The success probability of the proposed attacks is `1', while the complexity is negligible. In addition, we introduce two enhanced lightweight authentication protocols based on PUF chains (called PBAP and Salted PBAP), using the same design principles as PHEMAP and Salted PHEMAP. With the performance evaluation and the security analysis, it is justified that the two proposed schemes are practically well suited for use in resource-constrained IoT environments.
  • Publication
    Dynamic control of entropy and power consumption in TRNGs for IoT applications
    (Institute of Electronics, Information and Communication Engineers, 2018-01-25) Martín González, Honorio; San Millán Heredia, Enrique; Entrena Arrontes, Luis Alfonso; Ministerio de Economía y Competitividad (España)
    In this article we present a study about how to obtain a trade-off between two important metrics for IoT systems-Security vs Power Consumption. More specifically, we have studied how the min-entropy of two True-Random number generators can be adjusted dynamically in order to reduce the power consumption while guaranteeing the integrity of the system. To that end, we make use of some statistical tests that are typically used to measure the quality of the RNGs. Clock-gating and enable-gating are the selected techniques to reduce the power consumption.
  • Publication
    Influence of the AlN interlayer thickness on the photovoltaic properties of In-rich AlInN on Si heterojunctions deposited by RF sputtering
    (2018-11-14) Valdueza Felip, S.; Nuñez Cascajero, Arantzazu; Blasco, R.; Montero, D.; Grenet, L.; De La Mata, M.; Fernandez, S.; Rodriguez De Marcos, L.; Molina, S. I.; Olea, J.; Naranjo, F. B.; Comunidad de Madrid; Gobierno de España
  • Publication
    A lightweight implementation of the Tav-128 hash function
    (Institute of Electronics, Information and Communication Engineers, 2017-06-10) Martín González, Honorio; Peris López, Pedro; San Millán Heredia, Enrique; Estévez Tapiador, Juan Manuel
    In this article we discuss the hardware implementation of a lightweight hash function, named Tav-128 [1], which was purposely designed for constrained devices such as low-cost RFID tags. In the original paper, the authors only provide an estimation of the hardware complexity. Motivated for this, we describe both an ASIC and an FPGA-based implementation of the aforementioned cryptographic primitive, and examine the performance of three architectures optimizing different criteria: area, throughput, and a trade-off between both of them.
  • Publication
    A VCO-based CMOS readout circuit for capacitive MEMS microphones
    (MDPI, 2019-01-01) Quintero Alonso, Andrés; Cardes García, Fernando; Pérez Cruz, Carlos Andrés; Buffa, Cesare; Wiesbauer, Andreas; Hernández Corporales, Luis; Ministerio de Ciencia, Tecnología e Innovación (España)
    Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered 'always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta (SigmaDelta) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1/𝑓 and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 muA at 1.8 V and the effective area is 0.12 mm2. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.
  • Publication
    Full-resilient memory-optimum multi-party non-interactive key exchange
    (IEEE, 2020-02-06) Salimi, Majid; Mala, Hamid; Martín González, Honorio; Peris López, Pedro
    Multi-Party Non-Interactive Key Exchange (MP-NIKE) is a fundamental cryptographic primitive in which users register into a key generation centre and receive a public/private key pair each. After that, any subset of these users can compute a shared key without any interaction. Nowadays, IoT devices suffer from a high number and large size of messages exchanged in the Key Management Protocol (KMP). To overcome this, an MP-NIKE scheme can eliminate the airtime and latency of messages transferred between IoT devices. MP-NIKE schemes can be realized by using multilinear maps. There are several attempts for constructing multilinear maps based on indistinguishable obfuscation, lattices and the Chinese Remainder Theorem (CRT). Nevertheless, these schemes are inefficient in terms of computation cost and memory overhead. Besides, several attacks have been recently reported against CRT-based and lattice-based multilinear maps. There is only one modular exponentiation-based MP-NIKE scheme in the literature which has been claimed to be both secure and efficient. In this article, we present an attack on this scheme based on the Euclidean algorithm, in which two colluding users can obtain the shared key of any arbitrary subgroup of users. We also propose an efficient and secure MP-NIKE scheme. We show how our proposal is secure in the random oracle model assuming the hardness of the root extraction modulo a composite number.
  • Publication
    A true random number generator based on gait data for the Internet of You
    (IEEE, 2020-04-09) Cámara Núñez, María Carmen; Martín González, Honorio; Peris López, Pedro; Entrena Arrontes, Luis Alfonso
    The Internet of Things (IoT) is more and more a reality, and every day the number of connected objects increases. The growth is practically exponential -there are currently about 8 billion and expected to reach 21 billion in 2025. The applications of these devices are very diverse and range from home automation, through traffic monitoring or pollution, to sensors to monitor our health or improve our performance. While the potential of their applications seems to be unlimited, the cyber-security of these devices and their communications is critical for a flourishing deployment. Random Number Generators (RNGs) are essential to many security tasks such as seeds for key-generation or nonces used in authentication protocols. Till now, True Random Number Generators (TRNGs) are mainly based on physical phenomena, but there is a new trend that uses signals from our body (e.g., electrocardiograms) as an entropy source. Inspired by the last wave, we propose a new TRNG based on gait data (six 3-axis gyroscopes and accelerometers sensors over the subjects). We test both the quality of the entropic source (NIST SP800-90B) and the quality of the random bits generated (ENT, DIEHARDER and NIST 800-22). From this in-depth analysis, we can conclude that: 1) the gait data is a good source of entropy for random bit generation; 2) our proposed TRNG outputs bits that behave like a random variable. All this confirms the feasibility and the excellent properties of the proposed generator.
  • Publication
    Oversampled ADC based on pulse frequency modulator and TDC
    (IET, 2014-03) Hernández Corporales, Luis; Gutiérrez Fernández, Eric; Ministerio de Ciencia e Innovación (España)
    Oversaw led converters based on voltage controlled ring oscillators are an attractive solution because of their digital implementation and simplicity. However, the voltage-to-frequency conversion of ring oscillators displays a poor linearity. Replacing the ring oscillator by a pulse frequency modulator (PFM) that provides improved linearity at the expense of feedback and analogue amplification is proposed. Compared to the equivalent continuous time sigma delta modulators, the PFM may be more tolerant to circuit impairments. In addition, the output data of the proposed architecture is a multibit sequence through the use of a time-to-digital converter TDC instead of a Flash quantiser or a multibit digital-to-analogue converter. A high dynamic range can be achieved without severe constraints on analogue mismatch or clock jitter.
  • Publication
    Strategies to parallelize a finite element mesh truncation technique on multi-core and many-core architectures
    (Springer, 2023-05) Badía, José M.; Amor Martín, Adrián; Belloch Rodríguez, José Antonio; García Castillo, Luis Emilio; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España)
    Achieving maximum parallel performance on multi-core CPUs and many-core GPUs is a challenging task depending on multiple factors. These include, for example, the number and granularity of the computations or the use of the memories of the devices. In this paper, we assess those factors by evaluating and comparing different parallelizations of the same problem on a multiprocessor containing a CPU with 40 cores and four P100 GPUs with Pascal architecture. We use, as study case, the convolutional operation behind a non-standard finite element mesh truncation technique in the context of open region electromagnetic wave propagation problems. A total of six parallel algorithms implemented using OpenMP and CUDA have been used to carry out the comparison by leveraging the same levels of parallelism on both types of platforms. Three of the algorithms are presented for the first time in this paper, including a multi-GPU method, and two others are improved versions of algorithms previously developed by some of the authors. This paper presents a thorough experimental evaluation of the parallel algorithms on a radar cross-sectional prediction problem. Results show that performance obtained on the GPU clearly overcomes those obtained in the CPU, much more so if we use multiple GPUs to distribute both data and computations. Accelerations close to 30 have been obtained on the CPU, while with the multi-GPU version accelerations larger than 250 have been achieved.
  • Publication
    A pulse frequency modulation interpretation of VCOs enabling VCO-ADC architectures with extended noise shaping
    (IEEE, 2018-02) Gutiérrez Fernández, Eric; Hernández Corporales, Luis; Cardes García, Fernando; Rombouts, Pieter; Ministerio de Economía y Competitividad (España)
    In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order Delta Sigma modulators. A first advantage of our approach is that it unveils systematic error components not described by the equivalence with a conventional Delta Sigma modulator. A second advantage is that, by a proper selection of the pulses generated by the PFM, we can theoretically construct an open loop VCO-ADC with an arbitrary noise shaping order. Unfortunately, with the exception of the first-order noise shaping case, the required pulse waveforms cannot easily be implemented on the circuit level. However, we describe circuit techniques to achieve a good approximation of the required pulse waveforms, which can easily be implemented by practical circuits. Finally, our approach enables a straightforward description of multistage Delta Sigma modulator architectures, which is an alternative and practically feasible way to realize a VCO-ADC with extended noise shaping.
  • Publication
    An analysis of noise in multi-bit SigmaDelta modulators with low-frequency input signals
    (MDPI, 2022-10-01) Vera Sesmero, Pablo; Wiesbauer, Andreas; Patón Álvarez, Susana; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España)
    Digital and smart sensors are commonly implemented using multi-bit (Formula presented.) Modulators. Undesired signals can be present at the ADC input, such as low-frequency signals with medium or high amplitude, as a consequence of mechanical artifacts in the MEMS and/or temporary signal overload. Simulations and measurements of those sensors with such signals show temporary increments of in-band noise power. This paper investigates the factors that produce this transient performance loss. Interestingly, noise increments happen when the modulator is forced to toggle between three adjacent levels and is not correlated with the typical tonal behavior of (Formula presented.) Modulators. Hence, the sensor performance is sensitive to some specific input patterns even if tonal behavior is decreased by dithering the input of the ADC. Different error sources, such as the mismatch between DAC cells, loop filter linearity error, and quantization error, contribute to the observed noise increments. Our aim is to analyze each of these error sources to understand and quantify in-band noise power increments, and to desensitize the ADC from the undesired input patterns. Some estimation equations are proposed and verified through extensive simulations, by means of deterministic and stochastic methods. These equations are influenced by some modulator parameters and can be used to optimize them in order to reduce such in-band noise power increments.
  • Publication
    Reduced resolution redundancy: A novel approximate error mitigation technique
    (IEEE, 2022-02-16) García-Astudillo, Luis A.; Entrena Arrontes, Luis Alfonso; Lindoso Muñoz, Almudena; Martín González, Honorio; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España)
    Error mitigation techniques, such as Triple Modular Redundancy, introduce very large overheads. To alleviate this overhead, approximate techniques can be used. In this work we propose a novel approximate error mitigation technique based on using redundant circuits with lower resolution. As a representative case study, the approach is demonstrated for a Fast Fourier Transform, for which an optimized architecture is proposed. The approach is validated through fault injection. Experimental results show that Reduced Resolution Redundancy can significantly reduce the overhead and achieve an excellent error mitigation performance and a low sensitivity to uncorrectable errors.
  • Publication
    Analyzing Reduced Precision Triple Modular Redundancy under Proton Irradiation
    (IEEE, 2022-03-01) García Astudillo, Luis Ángel; Entrena Arrontes, Luis Alfonso; Lindoso Muñoz, Almudena; Martín González, Honorio; Martín-Holgado, Pedro; García Valderas, Mario; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España)
    This work analyzes the performance of the reduced precision redundancy (RPR) error mitigation technique using the fast Fourier transform (FFT) as a case study. To this purpose, several configurations of an FFT IP design were implemented in field-programmable gate array (FPGA) using reduced precision triple modular redundancy (RP-TMR) and tested under proton irradiation and fault injection. The cross section, the sensitivity to common-mode failures (CMFs), and the signal-to-noise ratio of these configurations were evaluated. The results of the radiation experiments and fault injection campaigns are in agreement and show that the RP-TMR technique may be used as an alternative to triple modular redundancy (TMR) if small errors can be tolerated, as it has a good performance in terms of error correction capabilities, area usage, and sensitivity to critical errors.
  • Publication
    Error sensitivity study of FFT architectures implemented in FPGA
    (Elsevier, 2021-11) García-Astudillo, L. A.; Lindoso Muñoz, Almudena; Entrena Arrontes, Luis Alfonso; Martín González, Honorio; García Valderas, Mario; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España)
    This work studies the impact that the architectural choices can have in the error mitigation of a digital processing module such as the Fast Fourier Transform. To this purpose, several serial and pipelined architectures were implemented in FPGA using Block Triple Modular Redundancy and analysed under a fault injection approach that was previously validated with radiation. These architectures were compared with respect to error rate, common mode failure rate and signal-to-noise ratio. Experimental results show that the error rate is strongly correlated with the use of resources when using a similar architecture. However, pipelined architectures tend to have more common mode failures but with lower signal-to-noise ratio than a serial architecture.
  • Publication
    Analyzing Scaled Reduced Precision Redundancy for Error Mitigation under Proton Irradiation
    (IEEE, 2022-07-01) García Astudillo, Luis Ángel; Lindoso Muñoz, Almudena; Entrena Arrontes, Luis Alfonso; Martín González, Honorio; García Valderas, Mario; Martín-Holgado, Pedro; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España)
    Reduced precision redundancy (RPR) is an alternative to triple modular redundancy (TMR) that reduces the area overhead at the expense of minor accuracy loss in case of error. In this work, we propose a Scaled RPR approach for multistage circuits and analyze the error mitigation tradeoffs. As a case study, several fast Fourier transform designs were tested with low-energy protons and fault injection. Experimental results show that the proposed approach achieves error mitigation with good accuracy, while significantly reducing the area overhead with respect to a full precision TMR approach.
  • Publication
    Bindi: Affective internet of things to combat gender-based violence
    (IEEE, 2022-11-01) Miranda Calero, José Ángel; Rituerto González, Esther; Luis Mingueza, Clara; Canabal Benito, Manuel Felipe; Ramírez Bárcenas, Alberto; Lanza Gutiérrez, José Manuel; Peláez Moreno, Carmen; López Ongil, Celia; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España); Universidad Carlos III de Madrid
    The main research motivation of this article is the fight against gender-based violence and achieving gender equality from a technological perspective. The solution proposed in this work goes beyond currently existing panic buttons, needing to be manually operated by the victims under difficult circumstances. Instead, Bindi, our end-to-end autonomous multimodal system, relies on artificial intelligence methods to automatically identify violent situations, based on detecting fear-related emotions, and trigger a protection protocol, if necessary. To this end, Bindi integrates modern state-of-the-art technologies, such as the Internet of Bodies, affective computing, and cyber-physical systems, leveraging: 1) affective Internet of Things (IoT) with auditory and physiological commercial off-the-shelf smart sensors embedded in wearable devices; 2) hierarchical multisensorial information fusion; and 3) the edge-fog-cloud IoT architecture. This solution is evaluated using our own data set named WEMAC, a very recently collected and freely available collection of data comprising the auditory and physiological responses of 47 women to several emotions elicited by using a virtual reality environment. On this basis, this work provides an analysis of multimodal late fusion strategies to combine the physiological and speech data processing pipelines to identify the best intelligence engine strategy for Bindi. In particular, the best data fusion strategy reports an overall fear classification accuracy of 63.61% for a subject-independent approach. Both a power consumption study and an audio data processing pipeline to detect violent acoustic events complement this analysis. This research is intended as an initial multimodal baseline that facilitates further work with real-life elicited fear in women.
  • Publication
    Multicore implementation of a multichannel parallel graphic equalizer
    (Springer, 2022-09) Belloch Rodríguez, José Antonio; Badía, José M.; León, Germán; Bank, Balázs; Välimäki, Vesa; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España); Universidad Carlos III de Madrid
    Numerous signal processing applications are emerging on mobile computing systems. These applications are subject to responsiveness constraints for user interactivity and, at the same time, must be optimized for energy efficiency. Many current embedded devices are composed of low-power multicore processors that offer a good trade-off between computational capacity and low power consumption. In this context, equalizers are widely used in multiple mobile-based applications such as "Music streaming" to adjust the levels of bass and treble in sound reproduction. In this study, we evaluate a graphic equalizer from audio, computational capacity, and energy efficiency perspectives, as well as the execution of multiple real-time equalizers running on an embedded quad-core processor of a mobile device. To this end, we experiment with the working frequencies as well as the parallelism that can be extracted from a quad-core ARM Cortex-A57. Results show that using high CPU frequencies and three or four cores, our parallel algorithm is able to equalize more than five channels per watt in real time with an audio buffer of 4096 samples, which implies a latency of 92.8 ms at the standard sample rate of 44.1 kHz.
  • Publication
    Time-encoding-based ultra-low power features extraction circuit for speech recognition tasks
    (MDPI, 2020-03) Gutiérrez Fernández, Eric; Pérez Cruz, Carlos Andrés; Hernández Ruiz, Fernando; Hernández Corporales, Luis; Ministerio de Ciencia e Innovación (España)
    Current trends towards on-edge computing on smart portable devices requires ultra-low power circuits to be able to make feature extraction and classification tasks of patterns. This manuscript proposes a novel approach for feature extraction operations in speech recognition/voice activity detection tasks suitable for portable devices. Whereas conventional approaches are based on either completely analog or digital structures, we propose a “hybrid” approach by means of voltage-controlled-oscillators. Our proposal makes use of a bank a band-pass filters implemented with ring-oscillators to extract the features (energy within different frequency bands) of input audio signals and digitize them. Afterwards, these data will input a digital classification stage such as a neural network. Ring-oscillators are structures with a digital nature, which makes them highly scalable with the possibility of designing them with minimum length devices. Additionally, due to their inherent phase integration, low-frequency band-pass filters can be implemented without large capacitors. Consequently, we strongly benefit from power consumption and area savings. Finally, our proposal may incorporate the analog-to-digital converter into the structure of the own features extractor circuit to make the full conversion of the raw data when triggered. This supposes a unique advantage with respect to other approaches. The architecture is described and proposed at system-level, along with behavioral simulations made to check whether the performance is the expected one or not. Then the structure is designed with a 65-nm CMOS process to estimate the power consumption and area on a silicon implementation. The results show that our solution is very promising in terms of occupied area with a competitive power consumption in comparison to other state-of-the-art solutions.
  • Publication
    Performance analysis of a millimeter wave MIMO channel estimation method in an embedded multi-core processor
    (Springer, 2022-08) Aviles Delgado, Pablo Miguel; Lloria, Diego; Belloch Rodríguez, José Antonio; Roger, Sandra; Lindoso Muñoz, Almudena; Cobos, Maximo; Comunidad de Madrid; Ministerio de Ciencia e Innovación (España)
    The emerging Multi-Processor System-on-Chip (MPSoC) technology, which combines heterogeneous computing with the high performance of field programmable gate arrays (FPGA), is a promising platform for a large number of applications, including wireless communications and vehicular technology. In this specific application context, when multiple-input multiple-output (MIMO) scenarios are considered, the system usually has to manage a large number of communication links among sensors and antennas involving different vehicles and users. Millimeter wave (mmWave) communications are one of the key technology enablers toward achieving high data rates in beyond 5G systems (B5G). Communication at these frequency bands usually involves the use of large antenna arrays, often requiring high computational resources. One of the candidate platforms able to manage a huge number of communications is the Xilinx Zynq UltraScale+ EG Heterogeneous MPSoC, which is composed of a dual-core Cortex-R5, a quad-core ARM Cortex-A53, a graphics processing unit (GPU) and a high-end FPGA. This work analyzes the computational performance that requires a recent mmWave MIMO channel estimation algorithm in a platform of this kind. As a first approach, we will focus our work on the performance that can be achieved via the quad-core ARM Cortex-A53. To this end, we will use the libraries for numerical algebra (BLAS and LAPACK). The results show that our reference implementation is able to manage a large MIMO communication system with 256 antennas without exhausting platform resources.
  • Publication
    VCO-based ADC with a simplified DAC for non-linearity correction
    (Institution of Engineering and Technology (IET), 2018-06) Quintero Alonso, Andrés; Pérez Cruz, Carlos Andrés; Gutiérrez Fernández, Eric; Hernández Corporales, Luis; Ministerio de Economía y Competitividad (España)
    The performance of open-loop ADCs implemented with VCOs is limited by VCO non-linearity and first-order noise shaping. The resolution limitation imposed by first-order noise shaping can be compensated by a ring oscillator VCO with many output phases. Linearity can also be improved by using a feedback loop around the VCO closed with a DAC. However, a long ring oscillator may require a DAC with a prohibitive number of bits if feedback is used to compensate distortion. This Letter proposes an ADC architecture based on the Leslie-Singh Sigma-Delta (Σ∆) modulator that allows to implement a distortion correction loop around a VCO with a simplified DAC of few levels, yet keeping a large number of output quantisation levels to maintain resolution. The Letter discusses the system-level architecture and shows an implementation circuit example to verify the effective correction of distortion.