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Reduced resolution redundancy: A novel approximate error mitigation technique

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URI: https://hdl.handle.net/10016/37122
ISSN: 2169-3536
DOI: https://doi.org/10.1109/ACCESS.2022.3152202
UXXI: AR/0000032590
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Reduced_IEEEA_2022.pdf (4.91 MB)
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2022-02-16
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IEEE
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Abstract
Error mitigation techniques, such as Triple Modular Redundancy, introduce very large overheads. To alleviate this overhead, approximate techniques can be used. In this work we propose a novel approximate error mitigation technique based on using redundant circuits with lower resolution. As a representative case study, the approach is demonstrated for a Fast Fourier Transform, for which an optimized architecture is proposed. The approach is validated through fault injection. Experimental results show that Reduced Resolution Redundancy can significantly reduce the overhead and achieve an excellent error mitigation performance and a low sensitivity to uncorrectable errors.
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Fault tolerance, Triple modular redundancy, Fast fourier transform, FPGA, Approximate computing
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Garcia-Astudillo, L. A., Entrena, L., Lindoso, A., & Martin, H. (2022). Reduced Resolution Redundancy: a Novel Approximate Error Mitigation Technique. IEEE Access, 10, 20643-20651.
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