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CCSDS 131.2-B-1 transmitter design on FPGA with adaptive coding and modulation schemes for satellite communications

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dc.affiliation.dptoUC3M. Departamento de Teoría de la Señal y Comunicacioneses
dc.affiliation.grupoinvUC3M. Grupo de Investigación: Comunicacioneses
dc.contributor.authorLamoral Coines, Adrian
dc.contributor.authorGil Jiménez, Víctor Pedro
dc.contributor.funderComunidad de Madrides
dc.contributor.funderMinisterio de Economía y Competitividad (España)es
dc.date.accessioned2022-02-22T12:59:43Z
dc.date.available2022-02-22T12:59:43Z
dc.date.issued2021-10-02
dc.description.abstractSatellite communications are a well-established research area in which the main innovation of last decade has been the use of multi-carrier modulations and more robust channel coding techniques. However, in recent years, novel advanced signal processing has started being developed for these communications due to the increase in the signal processing capacity of transmitters and receivers. Although signal processing capabilities are increasing, they are still constrained by large limitations because these techniques need to be implemented in real hardware, thus making complexity a matter of critical importance. Therefore, this paper presents the design and implementation of a transmitter with adaptable coding and modulation on a field-programmable-gate-array (FPGA). The main motivation came from the standard CCSDS 131.2-B-1 which recommends that such a novel transmitter which has to date not been implemented in a real system The system was modeled by MATLAB with the purpose of being programmed in VHDL following the AXI-stream protocol between components. Behavioral simulation results were obtained in VIVADO and compared with MATLAB for verification purposes. The transmitter logical circuit was synthesized in a FPGA Zynq Ultrascale RFSoC ZU28DR, showing low resource consumption and correct functioning, leading us to conclude that the deployment of new communication systems in state-of-the-art hardware in satellite communications is justified.en
dc.description.sponsorshipThe research was funded by Projects IRENE (PID2020-115323RB-C33) (MINECO/AEI/FEDER, UE) and MFOC (Madrid Flight on Chip "Innovation Cooperative Projects Comunidad of Madrid" HUBS 2018/ Madrid Flight on Chip).en
dc.format.extent17
dc.identifier.bibliographicCitationLamoral Coines, A. & Jiménez, V. P. G. (2021). CCSDS 131.2-B-1 Transmitter Design on FPGA with Adaptive Coding and Modulation Schemes for Satellite Communications. Electronics, 10(20), 2476.en
dc.identifier.doihttps://doi.org/10.3390/electronics10202476
dc.identifier.issn2079-9292
dc.identifier.publicationfirstpage2476
dc.identifier.publicationissue20
dc.identifier.publicationtitleElectronicsen
dc.identifier.publicationvolume10
dc.identifier.urihttps://hdl.handle.net/10016/34203
dc.identifier.uxxiAR/0000029217
dc.language.isoengen
dc.publisherMDPIen
dc.relation.projectIDGobierno de España. PID2020-115323RB-C33es
dc.rights© 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license.en
dc.rightsAtribución 3.0 España*
dc.rights.accessRightsopen accessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/es/*
dc.subject.ecienciaTelecomunicacioneses
dc.subject.otherFPGAen
dc.subject.otherRTLen
dc.subject.otherVHDLen
dc.subject.otherDSPen
dc.subject.otherSCCC turbo codeen
dc.subject.otherConstellation diagramen
dc.subject.otherPuncturingen
dc.subject.otherInterleaveren
dc.subject.otherPseudo-randomizeren
dc.titleCCSDS 131.2-B-1 transmitter design on FPGA with adaptive coding and modulation schemes for satellite communicationsen
dc.typeresearch article*
dc.type.hasVersionVoR*
dspace.entity.typePublication
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