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Autonomous fault emulation: a new FPGA-based acceleration system for hardness evaluation

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dc.affiliation.dptoUC3M. Departamento de Tecnología Electrónicaes
dc.affiliation.grupoinvUC3M. Grupo de Investigación: Diseño Microelectrónico y Aplicaciones (DMA)es
dc.contributor.authorLópez Ongil, Celia
dc.contributor.authorGarcía Valderas, Mario
dc.contributor.authorPortela García, Marta
dc.contributor.authorEntrena Arrontes, Luis Alfonso
dc.contributor.funderComunidad de Madrides
dc.contributor.funderMinisterio de Energía, Turismo y Agencia digital (España)es
dc.contributor.funderMinisterio de Industria (España)es
dc.date.accessioned2023-01-16T13:52:28Z
dc.date.available2023-01-16T13:52:28Z
dc.date.issued2007-02
dc.description.abstractThe appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past.en
dc.description.sponsorshipThis work was supported by the Directorate of Research of Madrid Community Government, Spain (Code 07/0052/2003 2) and by the European Commission and Spanish Government under MEDEA+ Project (PARACHUTE-2A701) and PROFIT Project (CIRCE-FIT-330100-2005-60).en
dc.format.extent10
dc.identifier.bibliographicCitationLopez-Ongil, C., Garcia-Valderas, M., Portela-Garcia, M. & Entrena, L. (2007). Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation. IEEE Transactions on Nuclear Science, 54(1), 252-261.en
dc.identifier.doihttps://doi.org/10.1109/TNS.2006.889115
dc.identifier.issn0018-9499
dc.identifier.publicationfirstpage252
dc.identifier.publicationissue1
dc.identifier.publicationlastpage261
dc.identifier.publicationtitleIEEE Transactions on Nuclear Scienceen
dc.identifier.publicationvolume54
dc.identifier.urihttps://hdl.handle.net/10016/36268
dc.identifier.uxxiAR/0000004213
dc.language.isoengen
dc.publisherIEEE
dc.relation.projectIDComunidad de Madrid. 07/0052/2003 2es
dc.relation.projectIDGobierno de España. TSI-020400-2008-22es
dc.relation.projectIDGobierno de España. FIT-330100-2005-60es
dc.rights© 2007, IEEE
dc.rights.accessRightsopen accessen
dc.subject.ecienciaElectrónicaes
dc.subject.otherFault emulationen
dc.subject.otherFault injectionen
dc.subject.otherFault toleranceen
dc.subject.otherFPGAen
dc.subject.otherReliability testingen
dc.subject.otherSEUen
dc.titleAutonomous fault emulation: a new FPGA-based acceleration system for hardness evaluationen
dc.typeresearch article*
dc.type.hasVersionAM*
dspace.entity.typePublication
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