Publication:
Processor Model for the Instruction Mapping Tool

Thumbnail Image
Identifiers
URI: https://hdl.handle.net/10016/22884
ISBN: 978-84-608-6309-0
Files
processor_mego_nesus_2016.pdf (315.38 KB)
Publication date
2016-02
Defense date
Authors
Advisors
Tutors
Journal Title
Journal ISSN
Volume Title
Publisher
Impact
Google Scholar
Export
Research Projects
Organizational Units
Journal Issue
Abstract
This paper describes the model designed for the instruction mapping tool, which can be used for generating the low level assembly code for the digital signal processing algorithms. The model is based on the Very Long Instruction Word architecture. The Texas Instrument TMS320C6678 was the pattern and finally was described with the created model. The paper is showing the parameters of the hardware resources and also the instruction set.
Description
Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016) Timisoara, Romania. February 8-11, 2016.
Keywords
Processor model, Instruction mapping, VLIW
Bibliographic citation
Carretero Pérez, Jesús; et.al. (eds.). (2016). Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016). Timisoara, Romania. Universidad Carlos III de Madrid, ARCOS. Pp. 41-44.
Collections
First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)