RT Conference Proceedings
T1 Processor Model for the Instruction Mapping Tool
A1 Mego, Roman
A2 Carretero Pérez, Jesús
A2 García Blas, Javier
A2 Petcu, Dana
AB This paper describes the model designed for the instruction mapping tool, which can be used for generating the lowlevel assembly code for the digital signal processing algorithms. The model is based on the Very Long InstructionWord architecture. The Texas Instrument TMS320C6678 was the pattern and finally was described with the createdmodel. The paper is showing the parameters of the hardware resources and also the instruction set.
SN 978-84-608-6309-0
YR 2016
FD 2016-02
LK https://hdl.handle.net/10016/22884
UL https://hdl.handle.net/10016/22884
LA eng
NO Proceedings of the First PhD Symposium on Sustainable UltrascaleComputing Systems (NESUS PhD 2016) Timisoara, Romania. February 8-11, 2016.
NO European Cooperation in Science and Technology. COST
DS e-Archivo
RD 25 may. 2024