Publication:
Processor Model for the Instruction Mapping Tool

Simple item page
dc.affiliation.dptoUC3M. Departamento de Informáticaes
dc.affiliation.grupoinvUC3M. Grupo de Investigación: Arquitectura de Computadores, Comunicaciones y Sistemases
dc.contributor.authorMego, Roman
dc.contributor.editorCarretero Pérez, Jesús
dc.contributor.editorGarcía Blas, Javier
dc.contributor.editorPetcu, Dana
dc.date.accessioned2016-04-29T07:39:50Z
dc.date.available2016-04-29T07:39:50Z
dc.date.issued2016-02
dc.descriptionProceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016) Timisoara, Romania. February 8-11, 2016.en
dc.description.abstractThis paper describes the model designed for the instruction mapping tool, which can be used for generating the low level assembly code for the digital signal processing algorithms. The model is based on the Very Long Instruction Word architecture. The Texas Instrument TMS320C6678 was the pattern and finally was described with the created model. The paper is showing the parameters of the hardware resources and also the instruction set.en
dc.description.sponsorshipEuropean Cooperation in Science and Technology. COSTen
dc.format.mimetypeapplication/pdf
dc.identifier.bibliographicCitationCarretero Pérez, Jesús; et.al. (eds.). (2016). Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016). Timisoara, Romania. Universidad Carlos III de Madrid, ARCOS. Pp. 41-44.en
dc.identifier.isbn978-84-608-6309-0
dc.identifier.publicationtitleProceedings of the First PhD Symposium on Sustainable UltrascaleComputing Systems (NESUS PhD 2016)en
dc.identifier.urihttps://hdl.handle.net/10016/22884
dc.language.isoeng
dc.relation.eventdateFebruary 8-11, 2016
dc.relation.eventnumber1
dc.relation.eventplaceTimisoara, Romaniaen
dc.relation.eventtitlePhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)en
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España
dc.rights.accessRightsopen access
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject.ecienciaInformáticaes
dc.subject.otherProcessor modelen
dc.subject.otherInstruction mappingen
dc.subject.otherVLIWen
dc.titleProcessor Model for the Instruction Mapping Toolen
dc.typeconference paper*
dc.type.hasVersionVoR*
dspace.entity.typePublication
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
processor_mego_nesus_2016.pdf
Size:
315.38 KB
Format:
Adobe Portable Document Format
Download
Collections
First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)