Publication: Automatic Cache Aware Roofline Model Building and Validation Using
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2016-12
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Abstract
The ever growing complexity of high performance computing systems imposes significant challenges to exploit as much as possible their computational and memory resources. Recently, the Cache-aware Roofline Model has gained popularity due to its simplicity when modeling multi-cores with complex memory hierarchy, characterizing applications bottlenecks, and quantifying achieved or remaining improvements. In this short paper we involve hardware locality topology detection to build the Cache Aware Roofline Model for modern processors in an open-source locality-aware tool. The proposed tool also includes a set of specific micro-benchmarks to assess the micro-architecture performance upper-bounds. The experimental results show that by relying on the proposed tool, it was possible to reach near-theoretical bounds of an Intel 3770K processor, thus proving the effectiveness of the modeling methodology.
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Proceedings of: Third International Workshop on Sustainable Ultrascale Computing Systems (NESUS 2016). Sofia (Bulgaria), October, 6-7, 2016.
Keywords
Roofline Model, DRAM, Cache, Tool, Cache Aware Roofline Model, Hw loc
Bibliographic citation
Carretero PĂ©rez, JesĂşs; et.al. (eds.). (2016) Proceedings of the Third International Workshop on Sustainable Ultrascale Computing Systems (NESUS 2016): Sofia, Bulgaria. Universidad Carlos III de Madrid, pp. 73-78