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Error-Tolerant Data Sketches using Approximate Nanoscale Memories and Voltage Scaling

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dc.affiliation.dptoUC3M. Departamento de Ingeniería Telemáticaes
dc.affiliation.grupoinvUC3M. Grupo de Investigación: Network Technologieses
dc.contributor.authorReviriego Vasallo, Pedro
dc.contributor.authorJunsangsri, Pilin
dc.contributor.authorLiu, Shanshan
dc.contributor.authorLombardi, Fabrizio
dc.contributor.funderComunidad de Madrides
dc.contributor.funderMinisterio de Ciencia, Innovación y Universidades (España)es
dc.date.accessioned2022-01-17T12:32:09Z
dc.date.available2023-12-31T00:00:05Z
dc.date.issued2021-12-31
dc.description.abstractData sketches (or summaries) are widely used to efficiently process large data sets and obtain relevant information, such as the number of distinct elements, their frequency or the similarity of several sets. Since sketches provide probabilistic estimates (hence accomplishing considerable reductions in storage and computational requirements), it seems that approximate hardware is appropriate for implementation providing an estimate rather than the exact value and enabling further improvements in metrics. In this paper, the use of voltage scaling in an approximate nanoscale FinFET-based memory for implementing sketches is studied and evaluated. To mitigate the errors introduced by the approximate memory, techniques to protect several widely used sketches when implemented in such voltage-scaled FinFET memory, are proposed. The proposed schemes preserve the sketches functionality with a negligible impact on the accuracy of their estimates and tolerate large bit error rates for sketches such as Minhash and HyperLogLog. The analysis and simulation results show that the intrinsic error tolerance of data sketches can be exploited to provide accurate estimates even when the memory suffers many errors due to the voltage scaling of the supply. Voltage scaling enables large power savings for Minhash and HyperLogLog. These initial results suggest that the use of approximate computing for data sketches is an interesting area for further research.en
dc.description.sponsorshipThis work was supported by the ACHILLES project PID2019-104207RB-I00 and the Go2Edge network RED2018-102585-T funded by the Spanish Agencia Estatal de Investigación (AEI) 10.13039/501100011033 and by the Madrid Community research project TAPIR-CM grant no. P2018/TCS-4496.en
dc.format.extent6
dc.identifier.bibliographicCitationIEEE Transactions on Nanotechnology. (2021), v. 21, pp. 16-22.en
dc.identifier.doihttps://doi.org/10.1109/TNANO.2021.3139394
dc.identifier.issn1536-125X
dc.identifier.publicationfirstpage16
dc.identifier.publicationlastpage22
dc.identifier.publicationtitleIEEE TRANSACTIONS ON NANOTECHNOLOGYen
dc.identifier.publicationvolume21
dc.identifier.urihttps://hdl.handle.net/10016/33888
dc.identifier.uxxiAR/0000029009
dc.language.isoengen
dc.publisherIEEEen
dc.relation.projectIDGobierno de España. PID2019-104207RB-I00/ACHILLESes
dc.relation.projectIDGobierno de España. RED2018-102585-Tes
dc.relation.projectIDComunidad de Madrid. P2018/TCS- 4496/TAPIR-CMes
dc.rights© 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.en
dc.rights.accessRightsopen accessen
dc.subject.ecienciaTelecomunicacioneses
dc.subject.otherData Sketchesen
dc.subject.otherApproximate computingen
dc.subject.otherError toleranceen
dc.subject.otherMemoriesen
dc.titleError-Tolerant Data Sketches using Approximate Nanoscale Memories and Voltage Scalingen
dc.typeresearch article*
dc.type.hasVersionAM*
dspace.entity.typePublication
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