Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs

Aranda, Luis Alberto; Reviriego Vasallo, Pedro; Maestro, Juan Antonio

Publication:
Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs

dc.affiliation.dpto	UC3M. Departamento de Ingeniería Telemática	es
dc.affiliation.grupoinv	UC3M. Grupo de Investigación: Network Technologies	es
dc.contributor.author	Aranda, Luis Alberto
dc.contributor.author	Reviriego Vasallo, Pedro
dc.contributor.author	Maestro, Juan Antonio
dc.date.accessioned	2023-11-27T16:54:06Z
dc.date.available	2023-11-27T16:54:06Z
dc.date.issued	2018-11-01
dc.description.abstract	Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some particular pixel caching structures such as line-buffer-based pipelines can be used to accelerate the filtering process. However, an SRAM-based FPGA implementation of these pipelines may have malfunctions due to the mentioned configuration memory errors, so an error mitigation technique is required. In this paper, a novel method to protect line-buffer-based pipelines against SRAM-based FPGA configuration memory errors is presented. Experimental results show that, using our protection technique, considerable savings in terms of FPGA resources can be achieved while maintaining the SEU protection coverage provided by other classic pipeline protection schemes.	en
dc.format.extent	10	es
dc.format.mimetype	application/pdf	en
dc.identifier.bibliographicCitation	Aranda, L., Reviriego, P., & Maestro, J. (2018). Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs. Electronics 7(11), p. 322.	en
dc.identifier.doi	10.3390/electronics7110322
dc.identifier.publicationissue	11	es
dc.identifier.publicationtitle	Electronics	en
dc.identifier.publicationvolume	7	es
dc.identifier.uri	https://hdl.handle.net/10016/38965
dc.identifier.uxxi	AR/0000022842
dc.language.iso	eng	en
dc.publisher	MDPI	en
dc.rights	© 2018 by the authors.	en
dc.rights	Atribución 3.0 España	*
dc.rights.accessRights	open access	en
dc.rights.uri	http://creativecommons.org/licenses/by/3.0/es/	*
dc.subject.eciencia	Telecomunicaciones	es
dc.subject.other	Image processing	en
dc.subject.other	Line buffer	en
dc.subject.other	Sram-based Fpga	en
dc.subject.other	Single event upset (Seu)	en
dc.subject.other	Configuration memory	en
dc.subject.other	Soft error	en
dc.title	Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs	en
dc.type	research article	*
dc.type.hasVersion	VoR	*
dspace.entity.type	Publication