Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes

dc.affiliation.dptoUC3M. Departamento de Ingeniería Telemáticaes
dc.affiliation.grupoinvUC3M. Grupo de Investigación: Network Technologieses
dc.contributor.authorLi, Jiaqiang
dc.contributor.authorReviriego Vasallo, Pedro
dc.contributor.authorXiao, Liyi
dc.contributor.authorWu, Haotian
dc.contributor.funderMinisterio de Economía y Competitividad (España)es
dc.contributor.funderComunidad de Madrides
dc.description.abstractAs technology scales, radiation induced soft errors create more complex error patterns in memories with a single particle corrupting several bits. This poses a challenge to the Error Correction Codes (ECCs) traditionally used to protect memories that can correct only single bit errors. During the last decade, a number of codes have been developed to correct the emerging error patterns, focusing initially on double adjacent errors and later on three bit burst errors. However, as the memory cells get smaller and smaller, the error patterns created by radiation will continue to change and thus new codes will be needed. In addition, the memory layout and the technology used may also make some patterns more likely than others. For example, in some memories, there maybe elements that separate blocks of bits in a word, making errors that affect two blocks less likely. Finally, for a given memory, depending on the data stored, some error patterns may be more critical than others. For example, if numbers are stored in the memory, in most cases, errors on the more significant bits have a larger impact. Therefore, for a given memory and application, to achieve optimal protection, we would like to have a code that corrects a given set of patterns. This is not possible today as there is a limited number of code choices available in terms of correctable error patterns and word lengths. However, most of the codes used to protect memories are linear block codes that have a regular structure and which design can be automated. In this paper, we propose the automation of error correction code design for memory protection. To that end, we introduce a software tool that given a word length and the error patterns that need to be corrected, produces a linear block code described by its parity check matrix and also the bit placement. The benefits of this automated design approach are illustrated with several case studies. Finally, the tool is made available so that designers can easily produce custom error correction codes for their specific needs.en
dc.description.sponsorshipJiaqiang Li and Liyi Xiao would like to acknowledge the support of the Fundamental Research Funds for the Central Universities (Grant No. HIT.KISTP.201404), Harbin science and innovation research special fund (2015RAXXJ003), and Special found for development of Shenzhen strategic emerging industries (JCYJ20150625142543456). Pedro Reviriego would like to acknowledge the support of the TEXEO project TEC2016-80339-R funded by the Spanish Ministry of Economy and Competitivity and of the Madrid Community research project TAPIR-CM Grant No. P2018/TCS-4496.en
dc.identifier.bibliographicCitationLi, J., Reviriego, P., Xiao, L. & Wu, H. (2021). Protecting Memories against Soft Errors: The Case for Customizable Error Correction Codes. IEEE Transactions on Emerging Topics in Computing, 9(2), pp. 651–663.en
dc.identifier.publicationtitleIEEE Transactions on Emerging Topics in Computingen
dc.relation.projectIDGobierno de España. TEC2016-80339-R
dc.relation.projectIDComunidad de Madrid. P2018/TCS-4496
dc.rights© 2021, IEEE
dc.rights.accessRightsopen accessen
dc.subject.otherBlock codesen
dc.subject.otherParity check codesen
dc.subject.otherError correctionen
dc.subject.otherIntegrated circuit reliabilityen
dc.subject.otherError correction codesen
dc.subject.otherSoft errorsen
dc.titleProtecting Memories against Soft Errors: The Case for Customizable Error Correction Codesen
dc.typeresearch article*
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