Publication: Implementación y análisis comparativo del rendimiento y eficiencia energética de un algoritmo de descompresión sobre FPGAs
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2012-05
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2012-05-07
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Abstract
Éste parte como trabajo futuro de otro proyecto en el que se implementó un algoritmo software de compresión de datos realizando un diseño teórico del mismo en lenguaje VHDL que se implementó en una FPGA. La idea inicial es implementar el algoritmo software de descompresión en una plataforma hardware mediante el lenguaje VHDL y realizar una evaluación del mismo sobre distintas plataformas. El descompresor consta de varios campos de tamaño totalmente configurable. Este proyecto forma parte del departamento de informática de la Universidad Carlos III de Madrid. El proyecto ha tenido distintas fases, la primera de ella es la implementación del algoritmo de descompresión en lenguaje VHDL, para ello ha utilizado el entorno de desarrollo Quartus II del fabricante Altera, ya que permite una rápida compilación y una simulación sencilla para verificar el correcto funcionamiento del diseño. Una vez el funcionamiento teórico es correcto se ha procedido a su implementación en la FPGA Nexys 2 de Digilent aunque posteriormente se han realizado pruebas con tres FPGAs distintas a esta, en este caso ha sido necesario el uso del entorno de desarrollo Xilinx Platform Studio (XPS) de Xilinx. Las FPGAs utilizadas son la Nexys 2, Nexys 3, Atlys (todas ellas de Digilent) y la Spartan 3A Starter Kit de Xilinx. Todas ellas constan de un microprocesador Microblaze que se ha configurado para que se encargue de la transmisión de datos al diseño en VHDL. El diseño en VHDL ha sido implementado en distintos coprocesadores, para que su funcionamiento sea totalmente independiente y modular. La conexión entre Microblaze y los distintos coprocesadores ha sido realizada mediante buses de comunicación FSL. Una vez se ha comprobado el correcto funcionamiento en FPGA se ha implementado en un mismo diseño el algoritmo de compresión y descompresión, así es posible evaluar si el algoritmo y ambos diseños son correctos. La comprobación ha sido satisfactoria por lo que se ha procedido a realizar pruebas de velocidad del diseño, consumo energético, comportamiento en distintas placas y comparación del coste hardware en cada FPGA tales como biestables, DCMs, LUTs y otros recursos. En último lugar se ha realizado un tutorial para ampliar los conocimientos del manejo del programa XPS, para permitir la comunicación mediante varios buses FSL desde Microblaze, lo que facilitará la implementación de futuros diseños. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
This project is an extension of an earlier project which implemented a compression data algorithm. The former one includes a theoretical design in VHDL language of the compression module and a practical implementation in an FPGA. The general idea of this project is to extend the previous project by implementing and testing a decompression algorithm in a hardware device using VHDL. The selected decompressor consists of several configurable modules; each one is responsible of compressing a particular field of the data. This project was developed in the department of computer science at the University Carlos III of Madrid. This project has different developing phases. The first one is the implementation of the decompression algorithm in VHDL language. We have used Quartus II framework from Altera, which performs fast hardware compilations and design simulations that allows to verify the correct design operation. In a second phase, we carried out a design implementation and testing in a FPGA Nexys 2 from Digilent. Then, this procedure was extended to other three different devices: Nexys 3, Atlys and Spartan 3A Starter Kit Xilinx. In these cases it has been necessary to use the Xilinx Platform Studio (XPS) framework from Xilinx. In overall, four different FPGAs were evaluated: Nexys 2, Nexys 3, Atlys (all three from Digilent) and Spartan 3A Starter Kit Xilinx. All of them consist of a Microblaze microprocessor that is configured to communicate with the co-processors (compressor/decompressor modules). The VHDL design has been implemented in these co-processors, so that its operation is totally independent and modular. The connection between Microblaze and the coprocessors has been performed using FSL communication buses. Once we have verified the correct operation on FPGAs, we evaluated the compression and decompression algorithms, so it is possible to evaluate whether the algorithm and both designs are properly working in each platform. Then we tested our design for different platform speeds, measuring the power consumption, the performance and the hardware costs: number of biestables, DCMs, LUTs, etc. Finally, this project includes a tutorial that extends the use of the XPS program. We introduce a methodology for performing communications through several FSL buses from Microblaze and coprocessors, which will simplify the design and implementation in future designs.
This project is an extension of an earlier project which implemented a compression data algorithm. The former one includes a theoretical design in VHDL language of the compression module and a practical implementation in an FPGA. The general idea of this project is to extend the previous project by implementing and testing a decompression algorithm in a hardware device using VHDL. The selected decompressor consists of several configurable modules; each one is responsible of compressing a particular field of the data. This project was developed in the department of computer science at the University Carlos III of Madrid. This project has different developing phases. The first one is the implementation of the decompression algorithm in VHDL language. We have used Quartus II framework from Altera, which performs fast hardware compilations and design simulations that allows to verify the correct design operation. In a second phase, we carried out a design implementation and testing in a FPGA Nexys 2 from Digilent. Then, this procedure was extended to other three different devices: Nexys 3, Atlys and Spartan 3A Starter Kit Xilinx. In these cases it has been necessary to use the Xilinx Platform Studio (XPS) framework from Xilinx. In overall, four different FPGAs were evaluated: Nexys 2, Nexys 3, Atlys (all three from Digilent) and Spartan 3A Starter Kit Xilinx. All of them consist of a Microblaze microprocessor that is configured to communicate with the co-processors (compressor/decompressor modules). The VHDL design has been implemented in these co-processors, so that its operation is totally independent and modular. The connection between Microblaze and the coprocessors has been performed using FSL communication buses. Once we have verified the correct operation on FPGAs, we evaluated the compression and decompression algorithms, so it is possible to evaluate whether the algorithm and both designs are properly working in each platform. Then we tested our design for different platform speeds, measuring the power consumption, the performance and the hardware costs: number of biestables, DCMs, LUTs, etc. Finally, this project includes a tutorial that extends the use of the XPS program. We introduce a methodology for performing communications through several FSL buses from Microblaze and coprocessors, which will simplify the design and implementation in future designs.
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Xilinx Platform Studio, FPGA (Field Programmable Gate Array), Coprocesador, Microblaze, FSL, Descompresión, Quartus II, Algoritmo