Publication: Implementación y evaluación de algoritmos de compresión en FPGAs
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2012-03
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2012-03-07
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Abstract
A partir de un algoritmo software de compresión de datos se ha realizado un diseño teórico del mismo en lenguaje VHDL que posteriormente ha sido implementado en un soporte hardware. La idea inicial era crear un algoritmo en VHDL que permitiera realizar una compresión simple de datos de tamaño de palabra arbitrario. Finalmente se amplió el diseño añadiendo nuevas líneas de código que permitieran implementar un nuevo algoritmo que realiza una doble compresión. Este proyecto ha sido realizado en el departamento de informática de la Universidad Carlos III de Madrid. En primer lugar el algoritmo en VHDL fue creado y probado en simulación mediante la herramienta Quartus II del fabricante Altera. Una vez que se comprobó su funcionamiento teórico se procedió a su implementación en la FPGA Spartan 3A del fabricante Xilinx. Para ello se ha utilizado el entorno de desarrollo Xilinx Platform Studio (XPS) también de Xilinx. La FPGA Spartan 3A viene integrada en la plataforma de desarrollo Spartan 3A Starter Kit. Dicha plataforma consta de un microprocesador MicroBlaze, el cual hemos configurado, y que se encarga del manejo de los datos. También hemos configurado una serie de dispositivos, denominados coprocesadores, encargados de realizar la compresión de datos. La conexión entre MicroBlaze y los coprocesadores se estable mediante buses de conexión llamados FSL. El correcto diseño y funcionamiento del modelo hardware creado se ha validado mediante diferentes pruebas realizadas utilizando diversas tramas de datos y comprobando que efectivamente la compresión de los datos era correcta. Igualmente se ha hecho un estudio del rendimiento y los costes hardware del diseño, tales como memoria, biestables, DCMs, etc. También se ha comparado el rendimiento de nuestro algoritmo con el rendimiento de un algoritmo software previamente existente. Finalmente se ha documentado un tutorial del manejo del programa XPS que permite una rápida familiarización con dicha herramienta para la implementación de futuros diseños en FPGA. _________________________________________________________________________________________________________________________
A theoretical design in VHDL language has been developed based on a software algorithm for data compression. This algorithm has subsequently been implemented in FPGAs devices. The initial idea was to create a VHDL algorithm that would make a simple compression of data of arbitrary word sizes. Finally, the design was extended implementing a new algorithm that performs a two phase compression. This project was performed at the Computer Science department of Carlos III University of Madrid. First, the VHDL algorithm was created and tested in a simulation using Quartus II tool from Altera. Once the theoretical performance was obtained, it was implemented in a FPGA Spartan 3A from Xilinx. We used the development environment called Xilinx Platform Studio (XPS) from Xilinx. The FPGA Spartan 3A is integrated into the development platform Spartan 3A Starter Kit. This platform consists of a MicroBlaze microprocessor, which we have set, and is responsible for managing the data. Also, we have set up several devices called coprocessors, responsible of carrying out the data compression. The connection between MicroBlaze and the coprocessors is established by FSL buses. The hardware implementation has been validated by several tests using various data sets and checks for ensuring that data compression was performed correctly. We have also made a study of the performance and hardware costs of the design, measuring the ammount of memory, number of flip-flops and DCMs, etc. Also, the performance of our algorithm has been compared with the performance of a software implementation of the algorithm. Finally we documented a management tutorial of XPS program that allows a fast familiarization with this tool for the implementation of future FPGA designs.
A theoretical design in VHDL language has been developed based on a software algorithm for data compression. This algorithm has subsequently been implemented in FPGAs devices. The initial idea was to create a VHDL algorithm that would make a simple compression of data of arbitrary word sizes. Finally, the design was extended implementing a new algorithm that performs a two phase compression. This project was performed at the Computer Science department of Carlos III University of Madrid. First, the VHDL algorithm was created and tested in a simulation using Quartus II tool from Altera. Once the theoretical performance was obtained, it was implemented in a FPGA Spartan 3A from Xilinx. We used the development environment called Xilinx Platform Studio (XPS) from Xilinx. The FPGA Spartan 3A is integrated into the development platform Spartan 3A Starter Kit. This platform consists of a MicroBlaze microprocessor, which we have set, and is responsible for managing the data. Also, we have set up several devices called coprocessors, responsible of carrying out the data compression. The connection between MicroBlaze and the coprocessors is established by FSL buses. The hardware implementation has been validated by several tests using various data sets and checks for ensuring that data compression was performed correctly. We have also made a study of the performance and hardware costs of the design, measuring the ammount of memory, number of flip-flops and DCMs, etc. Also, the performance of our algorithm has been compared with the performance of a software implementation of the algorithm. Finally we documented a management tutorial of XPS program that allows a fast familiarization with this tool for the implementation of future FPGA designs.
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Keywords
Algoritmos de compresión, VHDL (Lenguaje de descripción de material informático), Circuitos electrónicos