Peña Fernandez, ManuelSerrano-Cases, A.Lindoso Muñoz, AlmudenaGarcía Valderas, MarioEntrena Arrontes, Luis AlfonsoMartinez-Alvarez, A.Cuenca-Asensi, S.2021-05-202021-09-012019-09Peña-Fernández, M., Serrano-Cases, A., Lindoso, A., García-Valderas, M., Entrena, L., Martínez-Álvarez, A. & Cuenca-Asensi, S. (2019). Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection. Microelectronics Reliability, vol. 100-101, 113447.0026-2714https://hdl.handle.net/10016/32696This work presents a new Dual-Core LockStep approach to enhance fault tolerance in microprocessors. The proposed technique is based on the combination of software-based data checking and trace-based control-flow checking through an external hardware module. The hardware module is connected to the trace interface and is able to observe the execution of all the processors in the architecture. The proposed approach has been implemented for a dual core commercial processor. Experimental results demonstrate that the proposed technique has a high error detection capability with up to 99.63% error coverage.5eng© 2019 Elsevier Ltd.Atribución-NoComercial-SinDerivadas 3.0 Españaresearch articleElectrónicahttps://doi.org/10.1016/j.microrel.2019.113447open access113447Microelectronics Reliability100-101AR/0000024612