Shen, YukaiStraeussnigg, DietmarGutiérrez Fernández, Eric2023-08-222023-08-222023Shen, Y., Straeussnigg, D. & Gutierrez, E. (21-25 May 2023). Towards Ultra-Low Power Consumption VAD Architectures with Mixed Signal Circuits [proceedings]. 56th Edition IEEE ISCAS 2023: IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA.2158-1525https://hdl.handle.net/10016/38065Proceedings of: 56th Edition IEEE ISCAS 2023 - IEEE International Symposium on Circuits and Systems (ISCAS), 21-25 May 2023, Monterey, CA, USA.A voice activity detector architecture based on an analog feature extractor and a mixed signal classification stage is proposed for ultra-low power activity. The feature extraction stage is composed of a set of analog band-pass filters and frame energy estimators. The classification stage has a fully connected first layer built with ultra-low power consumption ring oscillators, followed by gated recurrent unit layers. The ring oscillator based layer consumes nWs according to transient simulations performed in a low power 65 nm CMOS technology. Additionally it features the ability to perform the analog-to-digital conversion required to handle subsequent GRU layers, as well as the possibility of computing a non-linear function like sigmoid seizing the intrinsic non-linearity of the ring oscillator. Training and testing operations are made proving competitive classification performance between a baseline model and our proposed architecture. In light of this, proper features for deployment on power-restricted edge-computing applications are shown.5eng© 2023 IEEE.Voice activity detection (VAD)Analog feature extractionRecurrent neural network (RNN)Gated recurrent unit (GRU)Ring oscillator (RO)conference proceedingsEducaciónElectrónicaTelecomunicacioneshttps://doi.org/10.1109/ISCAS46773.2023.10181669open access15Proceedings of 2023 IEEE International Symposium on Circuits and Systems (ISCAS)CC/0000034125