Peña Frenandez, M.Lindoso Muñoz, AlmudenaEntrena Arrontes, Luis AlfonsoGarcía Valderas, MarioPhilippe, S.Morilla, Y.Martin Holgado, P.2021-05-202021-05-202018-09Peña-Fernandez, M., Lindoso, A., Entrena, L., Garcia-Valderas, M., Philippe, S., Morilla, Y. & Martin-Holgado, P. (2018). PTM-based hybrid error-detection architecture for ARM microprocessors. Microelectronics Reliability, vol. 88-90, pp. 925–930.0026-2714https://hdl.handle.net/10016/32694This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS microprocessors because it does not modify the microprocessor architecture and is able to detect errors thanks to the reuse of its trace subsystem. Validation has been performed by proton irradiation and fault injection campaigns on a Zynq AP SoC including a Cortex-A9 ARM microprocessor and an implementation of the proposed hardware monitor in programmable logic. Experimental results demonstrate that a high error detection rate can be achieved on a commercial microprocessor.6eng© 2018 Elsevier Ltd.Atribución-NoComercial-SinDerivadas 3.0 Españaresearch articleElectrónicahttps://doi.org/10.1016/j.microrel.2018.07.074open access925930Microelectronics Reliability88-90AR/0000022768