RT Journal Article
T1 Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection
A1 Peña Fernandez, Manuel
A1 Serrano-Cases, A.
A1 Lindoso Muñoz, Almudena
A1 García Valderas, Mario
A1 Entrena Arrontes, Luis Alfonso
A1 Martinez-Alvarez, A.
A1 Cuenca-Asensi, S.
AB This work presents a new Dual-Core LockStep approach to enhance fault tolerance in microprocessors. The proposed technique is based on the combination of software-based data checking and trace-based control-flow checking through an external hardware module. The hardware module is connected to the trace interface and is able to observe the execution of all the processors in the architecture. The proposed approach has been implemented for a dual core commercial processor. Experimental results demonstrate that the proposed technique has a high error detection capability with up to 99.63% error coverage.
PB Elsevier
SN 0026-2714
YR 2019
FD 2019-09
LK https://hdl.handle.net/10016/32696
UL https://hdl.handle.net/10016/32696
LA eng
DS e-Archivo
RD 27 jul. 2024