RT Conference Proceedings
T1 Exploring OpenMP Accelerator Model in a real-life scientific application using hybrid CPU-MIC platforms
A1 Halbiniak, Kamil
A1 Szustak, Lukasz
A1 Lastovetsky, Alexey
A1 Wyrzykowski, Roman
A2 Carretero Pérez, Jesús
A2 García Blas, Javier
A2 Margenov, Svetozar
A2 Universidad Carlos III de Madrid. Computer Architecture, Communications and Systems Group (ARCOS)
AB The main goal of this paper is the suitability assessment of the OpenMP Accelerator Model (OMPAM) for porting a real-life scientific application to heterogeneous platforms containing a single Intel Xeon Phi coprocessor. This OpenMP extension is supported from version 4.0 of the standard, offering an unified directive-based programming model dedicated for massivelyparallel accelerators. In our study, we focus on applying the OMPAM extension together with the OpenMP tasks for a parallel application which implements the numerical model of alloy solidification. To map the application efficiently on target hybrid platforms using such constructs as omp target, omp target data and omp target update, we propose a decomposition of main tasks belonging to the computational core of the studied application. In consequence, the coprocessor is used to execute the major parallel workloads, while CPUs are responsible for executing a part of the application that do not require massively parallel resources. Effective overlapping computations with data transfers is another goal achieved in this way. The proposed approach allows us to execute the whole application 3.5 times faster than the original parallel version running on two CPUs.
SN 978-84-617-7450-0
YR 2016
FD 2016-12
LK https://hdl.handle.net/10016/24224
UL https://hdl.handle.net/10016/24224
LA eng
NO Proceedings of: Third International Workshop on Sustainable Ultrascale Computing Systems (NESUS 2016). Sofia (Bulgaria), October, 6-7, 2016.
NO This research was conducted with the support of COST Action IC1305 (NESUS), as well as the National Science Centre (Poland) under grant no. UMO-2011/03/B/ST6/03500. The authors are grateful to the Czestochowa University of Technology for granting access to Intel Xeon Phi coprocessors provided by the MICLAB project no. POIG.02.03.00.24-093/13 (http://miclab.pl).
DS e-Archivo
RD 1 jun. 2024