RT Journal Article
T1 Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs
A1 Aranda, Luis Alberto
A1 Reviriego Vasallo, Pedro
A1 Maestro, Juan Antonio
AB Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some particular pixel caching structures such as line-buffer-based pipelines can be used to accelerate the filtering process. However, an SRAM-based FPGA implementation of these pipelines may have malfunctions due to the mentioned configuration memory errors, so an error mitigation technique is required. In this paper, a novel method to protect line-buffer-based pipelines against SRAM-based FPGA configuration memory errors is presented. Experimental results show that, using our protection technique, considerable savings in terms of FPGA resources can be achieved while maintaining the SEU protection coverage provided by other classic pipeline protection schemes.
PB MDPI
YR 2018
FD 2018-11-01
LK https://hdl.handle.net/10016/38965
UL https://hdl.handle.net/10016/38965
LA eng
DS e-Archivo
RD 17 jul. 2024