RT Journal Article
T1 PTM-based hybrid error-detection architecture for ARM microprocessors
A1 Peña Frenandez, M.
A1 Lindoso Muñoz, Almudena
A1 Entrena Arrontes, Luis Alfonso
A1 García Valderas, Mario
A1 Philippe, S.
A1 Morilla, Y.
A1 Martin Holgado, P.
AB This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS microprocessors because it does not modify the microprocessor architecture and is able to detect errors thanks to the reuse of its trace subsystem. Validation has been performed by proton irradiation and fault injection campaigns on a Zynq AP SoC including a Cortex-A9 ARM microprocessor and an implementation of the proposed hardware monitor in programmable logic. Experimental results demonstrate that a high error detection rate can be achieved on a commercial microprocessor.
PB Elsevier
SN 0026-2714
YR 2018
FD 2018-09
LK https://hdl.handle.net/10016/32694
UL https://hdl.handle.net/10016/32694
LA eng
DS e-Archivo
RD 1 sept. 2024