Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer

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dc.contributor.author Palumbo, Alessandro
dc.contributor.author Cassano, Luca
dc.contributor.author Luzzi, Bruno
dc.contributor.author Hernández Gutiérrez, José Alberto
dc.contributor.author Reviriego Vasallo, Pedro
dc.contributor.author Bianchi, Giuseppe
dc.contributor.author Ottavi, Marco
dc.date.accessioned 2022-10-20T08:13:04Z
dc.date.issued 2022-07-01
dc.identifier.bibliographicCitation Palumbo, A., Cassano, L., Luzzi, B., Hernández, J. A., Reviriego, P., Bianchi, G. & Ottavi, M. (2022, julio). Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer. Journal of Systems Architecture, 128, 102543.
dc.identifier.issn 1383-7621
dc.identifier.uri http://hdl.handle.net/10016/35906
dc.description.abstract Software exploitable Hardware Trojan Horses (HTHs) inserted into commercial CPUs allow the attacker to run his/her own software or to gain unauthorized privileges. Recently a novel menace raised: HTHs inserted by CAD tools. A consequence of such scenario is that HTHs must be considered a serious threat not only by academy but also by industry. In this paper we try to answer to the following question: can Machine Learning (ML) help designers of microprocessor softcores implemented onto SRAM-based FPGAs at detecting HTHs introduced by the employed CAD tool during the generation of the bitstream? We present a comparative analysis of the ability of several ML models at detecting the presence of HTHs in the bitstream by exploiting a previously performed characterization of the microprocessor softcore and an associated ML training. An experimental analysis has been carried out targeting the IBEX RISC-V microprocessor running a set of benchmark programs. A detailed comparison of multiple ML models is conducted, showing that many of them achieve accuracy above 98%, and kappa values above 0.97. By identifying the most effective ML models and the best features to be employed, this paper lays the foundation for the integration of a ML-based bitstream verification flow.
dc.description.sponsorship J. A. Hernández and P. Reviriego acknowledge the ACHILLES PID2019-104207RB-I00 and 6G-INTEGRATION-3-TSI-063000-2021-127 projects and the Go2Edge RED2018-102585-T network funded by the Spanish Agencia Estatal de Investigación (AEI) 10.13039/501100011033 and the Madrid Community research project TAPIR-CM grant no. P2018/TCS-4496.
dc.format.extent 11
dc.language.iso eng
dc.publisher Elsevier
dc.rights © 2022 Elsevier B.V. All rights reserved.
dc.rights Atribución-NoComercial-SinDerivadas 3.0 España
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subject.other CAD
dc.subject.other Hardware security
dc.subject.other Hardware trojans
dc.subject.other Machine learning
dc.subject.other Microprocessors
dc.subject.other RISC-V
dc.subject.other SRAM-based FPGA
dc.title Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
dc.type research article
dc.subject.eciencia Informática
dc.identifier.doi https://doi.org/10.1016/j.sysarc.2022.102543
dc.rights.accessRights embargoed access
dc.relation.projectID Comunidad de Madrid. S2018/TCS-4496
dc.relation.projectID Gobierno de España. PID2019-104207RB-I00
dc.relation.projectID Gobierno de España. TSI-063000-2021-127
dc.relation.projectID Gobierno de España. RED2018-102585-T
dc.identifier.publicationfirstpage 1
dc.identifier.publicationlastpage 11
dc.identifier.publicationtitle Journal of Systems Architecture
dc.identifier.publicationvolume 128
dc.identifier.uxxi AR/0000030705
carlosiii.embargo.liftdate 2024-07-01
carlosiii.embargo.terms 2024-07-01
dc.contributor.funder Comunidad de Madrid
dc.contributor.funder Agencia Estatal de Investigación (España)
dc.affiliation.dpto UC3M. Departamento de Ingeniería Telemática
dc.affiliation.grupoinv UC3M. Grupo de Investigación: Network Technologies
dc.type.hasVersion AM
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