Dimensioning an FPGA for real-time implementation of state of the art neural network-based hpa predistorter

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dc.contributor.author Louliej, Abdelhamid
dc.contributor.author Jabrane, Younes
dc.contributor.author Gil Jiménez, Víctor Pedro
dc.contributor.author Guilloud, Frédéric
dc.date.accessioned 2022-03-14T08:58:06Z
dc.date.available 2022-03-14T08:58:06Z
dc.date.issued 2021-07-01
dc.identifier.bibliographicCitation Louliej, A., Jabrane, Y., Jiménez, V. P. G., & Guilloud, F. (2021). Dimensioning an FPGA for Real-Time Implementation of State of the Art Neural Network-Based HPA Predistorter. Electronics, 10(13)
dc.identifier.issn 2079-9292
dc.identifier.uri http://hdl.handle.net/10016/34341
dc.description.abstract Orthogonal Frequency Division Multiplexing (OFDM) is one of the key modulations for current and novel broadband communications standards. For example, Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) is an excellent choice for the ECMA-368 Ultra Wide-band (UWB) wireless communication standard. Nevertheless, the high Peak to Average Power Ratio (PAPR) of MB-OFDM UWB signals reduces the power efficiency of the key element in mobile devices, the High Power Amplifier (HPA), due to non-linear distortion, known as the non-linear saturation of the HPA. In order to deal with this limiting problem, a new and efficient pre-distorter scheme using a Neural Networks (NN) is proposed and also implemented on Field Programmable Gate Array (FPGA). This solution based on the pre-distortion concept of HPA non-linearities offers a good trade-off between complexity and performance. Some tests and validation have been conducted on the two types of HPA: Travelling Wave Tube Amplifiers (TWTA) and Solid State Power Amplifiers (SSPA). The results show that the proposed pre-distorter design presents low complexity and low error rate. Indeed, the implemented architecture uses 10% of DSP (Digital Signal Processing) blocks and 1% of LUTs (Look up Table) in case of SSPA, whereas it only uses 1% of LUTs in case of TWTA. In addition, it allows us to conclude that advanced machine learning techniques can be efficiently implemented in hardware with the adequate design.
dc.description.sponsorship This work was partly funded by projects TERESA-ADA (TEC2017-90093-C3-2-R) (MINECO/ AEI/FEDER, UE) and MFOC (Madrid Flight on Chip—Innovation Cooperative Projects Comunidad of Madrid—HUBS 2018/MadridFlightOnChip).
dc.format.extent 15
dc.language.iso eng
dc.publisher MDPI
dc.rights © 2021 by the authors.
dc.rights Atribución 3.0 España
dc.rights.uri http://creativecommons.org/licenses/by/3.0/es/
dc.subject.other ECMA-368
dc.subject.other MB-OFDM
dc.subject.other HPA
dc.subject.other PAPR
dc.subject.other Pre-distortion
dc.subject.other Neural networks
dc.subject.other FPGA
dc.title Dimensioning an FPGA for real-time implementation of state of the art neural network-based hpa predistorter
dc.type article
dc.subject.eciencia Ingeniería Industrial
dc.identifier.doi https://doi.org/10.3390/electronics10131538
dc.rights.accessRights openAccess
dc.relation.projectID Gobierno de España. TEC2017-90093-C3-2-R
dc.relation.projectID Comunidad de Madrid. HUBS 2018/MadridFlightOnChip
dc.type.version publishedVersion
dc.identifier.publicationfirstpage 1
dc.identifier.publicationissue 13
dc.identifier.publicationlastpage 15
dc.identifier.publicationtitle Electronics (Switzerland)
dc.identifier.publicationvolume 10
dc.identifier.uxxi AR/0000028832
dc.contributor.funder Comunidad de Madrid
dc.contributor.funder Ministerio de Economía y Competitividad (España)
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