CCSDS 131.2-B-1 transmitter design on FPGA with adaptive coding and modulation schemes for satellite communications

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Show simple item record Lamoral Coines, Adrian Gil Jiménez, Víctor Pedro 2022-02-22T12:59:43Z 2022-02-22T12:59:43Z 2021-10-02
dc.identifier.bibliographicCitation Lamoral Coines, A. & Jiménez, V. P. G. (2021). CCSDS 131.2-B-1 Transmitter Design on FPGA with Adaptive Coding and Modulation Schemes for Satellite Communications. Electronics, 10(20), 2476.
dc.identifier.issn 2079-9292
dc.description.abstract Satellite communications are a well-established research area in which the main innovation of last decade has been the use of multi-carrier modulations and more robust channel coding techniques. However, in recent years, novel advanced signal processing has started being developed for these communications due to the increase in the signal processing capacity of transmitters and receivers. Although signal processing capabilities are increasing, they are still constrained by large limitations because these techniques need to be implemented in real hardware, thus making complexity a matter of critical importance. Therefore, this paper presents the design and implementation of a transmitter with adaptable coding and modulation on a field-programmable-gate-array (FPGA). The main motivation came from the standard CCSDS 131.2-B-1 which recommends that such a novel transmitter which has to date not been implemented in a real system The system was modeled by MATLAB with the purpose of being programmed in VHDL following the AXI-stream protocol between components. Behavioral simulation results were obtained in VIVADO and compared with MATLAB for verification purposes. The transmitter logical circuit was synthesized in a FPGA Zynq Ultrascale RFSoC ZU28DR, showing low resource consumption and correct functioning, leading us to conclude that the deployment of new communication systems in state-of-the-art hardware in satellite communications is justified.
dc.description.sponsorship The research was funded by Projects IRENE (PID2020-115323RB-C33) (MINECO/AEI/FEDER, UE) and MFOC (Madrid Flight on Chip "Innovation Cooperative Projects Comunidad of Madrid" HUBS 2018/ Madrid Flight on Chip).
dc.format.extent 17
dc.language.iso eng
dc.publisher MDPI
dc.rights © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license.
dc.rights Atribución 3.0 España
dc.subject.other FPGA
dc.subject.other RTL
dc.subject.other VHDL
dc.subject.other DSP
dc.subject.other SCCC turbo code
dc.subject.other Constellation diagram
dc.subject.other Puncturing
dc.subject.other Interleaver
dc.subject.other Pseudo-randomizer
dc.title CCSDS 131.2-B-1 transmitter design on FPGA with adaptive coding and modulation schemes for satellite communications
dc.type article
dc.subject.eciencia Telecomunicaciones
dc.rights.accessRights openAccess
dc.relation.projectID Gobierno de España. PID2020-115323RB-C33
dc.type.version publishedVersion
dc.identifier.publicationfirstpage 2476
dc.identifier.publicationissue 20
dc.identifier.publicationtitle Electronics
dc.identifier.publicationvolume 10
dc.identifier.uxxi AR/0000029217
dc.contributor.funder Comunidad de Madrid
dc.contributor.funder Ministerio de Economía y Competitividad (España)
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