Error-Tolerant Data Sketches using Approximate Nanoscale Memories and Voltage Scaling

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Show simple item record Reviriego Vasallo, Pedro Junsangsri, Pilin Liu, Shanshan Lombardi, Fabrizio 2022-01-17T12:32:09Z 2021-12-31
dc.identifier.bibliographicCitation IEEE Transactions on Nanotechnology. (2021), v. 21, pp. 16-22.
dc.identifier.issn 1536-125X
dc.description.abstract Data sketches (or summaries) are widely used to efficiently process large data sets and obtain relevant information, such as the number of distinct elements, their frequency or the similarity of several sets. Since sketches provide probabilistic estimates (hence accomplishing considerable reductions in storage and computational requirements), it seems that approximate hardware is appropriate for implementation providing an estimate rather than the exact value and enabling further improvements in metrics. In this paper, the use of voltage scaling in an approximate nanoscale FinFET-based memory for implementing sketches is studied and evaluated. To mitigate the errors introduced by the approximate memory, techniques to protect several widely used sketches when implemented in such voltage-scaled FinFET memory, are proposed. The proposed schemes preserve the sketches functionality with a negligible impact on the accuracy of their estimates and tolerate large bit error rates for sketches such as Minhash and HyperLogLog. The analysis and simulation results show that the intrinsic error tolerance of data sketches can be exploited to provide accurate estimates even when the memory suffers many errors due to the voltage scaling of the supply. Voltage scaling enables large power savings for Minhash and HyperLogLog. These initial results suggest that the use of approximate computing for data sketches is an interesting area for further research.
dc.description.sponsorship This work was supported by the ACHILLES project PID2019-104207RB-I00 and the Go2Edge network RED2018-102585-T funded by the Spanish Agencia Estatal de Investigación (AEI) 10.13039/501100011033 and by the Madrid Community research project TAPIR-CM grant no. P2018/TCS-4496.
dc.format.extent 6
dc.language.iso eng
dc.publisher IEEE
dc.rights © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
dc.subject.other Data Sketches
dc.subject.other Approximate computing
dc.subject.other Error tolerance
dc.subject.other Memories
dc.title Error-Tolerant Data Sketches using Approximate Nanoscale Memories and Voltage Scaling
dc.type article
dc.subject.eciencia Telecomunicaciones
dc.rights.accessRights embargoedAccess
dc.relation.projectID Gobierno de España. PID2019-104207RB-I00/ACHILLES
dc.relation.projectID Gobierno de España. RED2018-102585-T
dc.relation.projectID Comunidad de Madrid. P2018/TCS- 4496/TAPIR-CM
dc.type.version acceptedVersion
dc.identifier.publicationfirstpage 16
dc.identifier.publicationlastpage 22
dc.identifier.publicationtitle IEEE TRANSACTIONS ON NANOTECHNOLOGY
dc.identifier.publicationvolume 21
dc.identifier.uxxi AR/0000029009
carlosiii.embargo.liftdate 2023-12-31
carlosiii.embargo.terms 2023-12-31
dc.contributor.funder Comunidad de Madrid
dc.contributor.funder Ministerio de Ciencia, Innovación y Universidades (España)
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