Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

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dc.contributor.author Butt, Uzma M.
dc.contributor.author Khan, Shoab A.
dc.contributor.author Ullah, Anees
dc.contributor.author Khaliq, Abdul
dc.contributor.author Reviriego Vasallo, Pedro
dc.contributor.author Zahir, Ali
dc.date.accessioned 2021-07-20T10:27:23Z
dc.date.available 2021-07-20T10:27:23Z
dc.date.issued 2021-08
dc.identifier.bibliographicCitation Butt, U. M., Khan, S. A., Ullah, A., Khaliq, A., Reviriego, P. & Zahir, A. (2021). Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(8), pp. 3351–3362.
dc.identifier.issn 1549-8328
dc.identifier.uri http://hdl.handle.net/10016/33114
dc.description.abstract The estimation of the Direction of Arrival (DoA) is one of the most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) is a powerful technique for DoA estimation. The algorithm requires complex mathematical operations like the computation of the covariance matrix for the input signals, eigenvalue decomposition and signal peak search. All these signal processing operations make real-time and resource-efficient implementation of the MUSIC algorithm on Field Programmable Gate Arrays (FPGAs) a challenge. In this paper, a novel design approach is proposed for the FPGA-implementation of the MUSIC algorithm. This approach enables a significant reduction in both FPGA resources and latency. In more detail, the proposed design enables the estimation of DoA in real-time scenarios in 2μ sec with 30% to 50% fewer resources as compared to existing techniques.
dc.description.sponsorship The work of Pedro Reviriego was supported in part by the Architecting Intelligent Cost-effective Central Offices to enable 5G Tactile Internet (ACHILLES) through the Spanish Ministry of Economy and Competitivity under Project PID2019-104207RB-I00, in part by the Madrid Government (Comunidad de Madrid-Spain) through the Multiannual Agreement with Universidad Carlos III de Madrid (UC3M) in the line of Excellence of University Professors under Grant EPUC3M21, and in part by the Context of the V Plan Regional de Investigación Científica e Innovación Tecnológica (V PRICIT) (Regional Program of Research and Technological Innovation).
dc.format.extent 12
dc.language.iso eng
dc.publisher IEEE
dc.rights © 2021, IEEE
dc.subject.other Direction of arrival
dc.subject.other Music
dc.subject.other Array signal processing
dc.subject.other FPGA
dc.title Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation
dc.type article
dc.subject.eciencia Telecomunicaciones
dc.identifier.doi https://doi.org/10.1109/TCSI.2021.3083280
dc.rights.accessRights openAccess
dc.relation.projectID Gobierno de España. PID2019-104207RB-I00
dc.relation.projectID Comunidad de Madrid. EPUC3M21
dc.type.version acceptedVersion
dc.identifier.publicationfirstpage 3351
dc.identifier.publicationissue 8
dc.identifier.publicationlastpage 3362
dc.identifier.publicationtitle IEEE Transactions on Circuits and Systems I: Regular Papers
dc.identifier.publicationvolume 68
dc.identifier.uxxi AR/0000027900
dc.contributor.funder Comunidad de Madrid
dc.contributor.funder Ministerio de Ciencia e Innovación (España)
dc.contributor.funder Universidad Carlos III de Madrid
dc.affiliation.dpto UC3M. Departamento de Ingeniería Telemática
dc.affiliation.grupoinv UC3M. Grupo de Investigación: Network Technologies
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