Publication: Diseño de un módulo observador para un microprocesador ARM9 en un SOPC
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2016-09-26
Defense date
2016-10-04
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Abstract
En este Trabajo de Fin de Grado se aborda el diseño de un módulo hardware capaz
de observar el flujo de ejecución de un microprocesador ARM Cortex-A9, con el que
poder detectar errores en su funcionamiento. Para ello ha sido necesario un profundo
estudio y comprensión del subsistema ARM CoreSight donde se integra la interfaz de
traza utilizada en la observación, así como su posterior configuración y pruebas de
funcionamiento.
La necesidad de este desarrollo se enmarca en el creciente problema que suponen los
errores transitorios (en inglés soft errors) para el funcionamiento de los circuitos
digitales. Es un problema tan antiguo como la electrónica, ya que tiene su principal
causa en las interferencias producidas por radiación cósmica y electromagnética, y
existen técnicas (denominadas “hardening” o endurecimiento) para aumentar su
tolerancia a fallos desde la época de la carrera espacial.
De un tiempo a esta parte, los grandes avances realizados en las tecnologías de silicio
han propiciado notables incrementos tanto en sus prestaciones como en la eficiencia
energética asociada, ampliando los sectores de aplicación de los microprocesadores. Sin
embargo, la gran complejidad y densidad de integración asociadas, hace a las nuevas
generaciones de microprocesadores cada vez más vulnerables a estos errores ya no
solamente a nivel aeroespacial, sino también en aplicaciones terrestres.
En cualquier sistema electrónico la fiabilidad es fundamental, y más si se utiliza en
una aplicación crítica para la seguridad. Aparece, por tanto, la necesidad de renovar las
técnicas de endurecimiento y adaptarlas a las nuevas necesidades, distinguiéndose tres
categorías: técnicas hardware, software e híbridas. De ellas, las más efectivas son las
técnicas hardware, sin embargo requieren un exhaustivo conocimiento del circuito a
robustecer, información que no siempre se encuentra disponible en el ámbito del
mercado de la electrónica de consumo; en el que ARM tiene una posición dominante.
In this Bachelor Thesis, the design of a hardware module capable of observe the execution of an ARM Cortex-A9 is addressed, with the aim of detecting operation errors. A deep study and comprehension of ARM CoreSight subsystem has been needed, that integrates the trace interface used in observations. Also, operation tests and configurations have been done. This work is related with the rising problem involving soft errors in the digital circuits’ normal behavior. This problem is as old as electronics, and has its main cause in cosmic and electromagnetic radiation interferences. Hardening techniques have been developed in order to increase the associated fault-tolerance since the space race. In the past few years, great advances made in silicon technologies have promoted big growth both in performance as in energy efficiency. Thus, application sectors for microprocessors have been expanded. However, the big complexity and integration density reached make new processor’s generations even more vulnerable to soft errors, not only in space but also at ground level. Reliability is a must in every electronic system, more if it’s used for safety-critical applications. Therefore, the need to renew or adapt hardening techniques to new needs, appear. Three different categories can be applied: hardware techniques, software and hybrid ones. Among them, the most effective ones are hardware ones, but they require a deep knowledge about the hardened circuit. This information is not always available in consumer electronics market, in which ARM has a privileged position.
In this Bachelor Thesis, the design of a hardware module capable of observe the execution of an ARM Cortex-A9 is addressed, with the aim of detecting operation errors. A deep study and comprehension of ARM CoreSight subsystem has been needed, that integrates the trace interface used in observations. Also, operation tests and configurations have been done. This work is related with the rising problem involving soft errors in the digital circuits’ normal behavior. This problem is as old as electronics, and has its main cause in cosmic and electromagnetic radiation interferences. Hardening techniques have been developed in order to increase the associated fault-tolerance since the space race. In the past few years, great advances made in silicon technologies have promoted big growth both in performance as in energy efficiency. Thus, application sectors for microprocessors have been expanded. However, the big complexity and integration density reached make new processor’s generations even more vulnerable to soft errors, not only in space but also at ground level. Reliability is a must in every electronic system, more if it’s used for safety-critical applications. Therefore, the need to renew or adapt hardening techniques to new needs, appear. Three different categories can be applied: hardware techniques, software and hybrid ones. Among them, the most effective ones are hardware ones, but they require a deep knowledge about the hardened circuit. This information is not always available in consumer electronics market, in which ARM has a privileged position.
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Keywords
Microprocesador ARM Cortex-A9, Tolerancia a fallos, Endurecimiento, Interfaz de traza, Errores transitorios