Processor Model for the Instruction Mapping Tool

Mego, Roman

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Processor Model for the Instruction Mapping Tool

Author(s): Mego, Roman

Editor: Carretero Pérez, Jesús
García Blas, Javier
Petcu, Dana

Issued date: 2016-02

Citation: Carretero Pérez, Jesús; et.al. (eds.). (2016). Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016). Timisoara, Romania. Universidad Carlos III de Madrid, ARCOS. Pp. 41-44.

ISBN: 978-84-608-6309-0

Sponsor: European Cooperation in Science and Technology. COST

Keywords: Processor model , Instruction mapping , VLIW

URI: http://hdl.handle.net/10016/22884

Rights: Atribución-NoComercial-SinDerivadas 3.0 España

Abstract:

This paper describes the model designed for the instruction mapping tool, which can be used for generating the low level assembly code for the digital signal processing algorithms. The model is based on the Very Long Instruction Word architecture. The Texas [+]