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Processor Model for the Instruction Mapping Tool
Autor(es):
Mego, Roman
Editor:
Carretero Pérez, Jesús
García Blas, Javier
Petcu, Dana
García Blas, Javier
Petcu, Dana
Fecha de edición:
2016-02
Cita:
Carretero Pérez, Jesús; et.al. (eds.). (2016). Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016). Timisoara, Romania. Universidad Carlos III de Madrid, ARCOS. Pp. 41-44.
ISBN:
978-84-608-6309-0
Patrocinador:
European Cooperation in Science and Technology. COST
Palabras clave:
Processor model
,
Instruction mapping
,
VLIW
Derechos:
Atribución-NoComercial-SinDerivadas 3.0 España
Resumen:
This paper describes the model designed for the instruction mapping tool, which can be used for generating the low
level assembly code for the digital signal processing algorithms. The model is based on the Very Long Instruction
Word architecture. The Texas
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Nota:
Proceedings of the First PhD Symposium on Sustainable Ultrascale
Computing Systems (NESUS PhD 2016) Timisoara, Romania. February 8-11, 2016.
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