Publication: Contribution to the design of Capacitance-to-Digital Converters for medium-resolution multi-standard consumer sensors in standard CMOS technology
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2020-03
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2020-03-06
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Abstract
Capacitive sensors are omnipresent in both automotive and consumer applications. Micro-Electro-
Mechanical-Systems (MEMS) are often used to transform a physical quantity (e.g. pressure, temperature,
humidity, ...) to electrical quantities (e.g. capacitance, resistance, ...). Capacitanceto-Digital Converters (CDCs) are therefore of major significance. They permanently strive for
perfection since they represent the State-of-the-Art in terms of an e cient electrical interface and
adequate digital conversion of those capacitive sensors.
The purpose of this research is to provide new insights into a specific converter family in the
context of a CDC. While a vast amount of converter concepts has been discussed in the open
literature, this dissertation focuses on a simplified type of time-domain converter. To be more
specific, a Dual-Slope based Capacitance-to-Digital Converter is presented. The traditional Dual-
Slope converter is modified to provide a switched-capacitor sensor readout, first-order noise-shaping
and e cient multi-bit conversion using single-bit circuitry. It is based on an averaging concept and
employs a kind of time-domain resolution. A similar concept was already shown in the past. It
was based on a continuous-time converter using a dedicated sensor readout stage. It is important
to point out that this new dissertation focuses on a direct sensor readout concept to utilize the
discrete-time benefits. As a result, both area and power e ciency are improved.
The converter concept is proven on silicon in a standard 0.13 m process using both a real
capacitive pressure sensor and an on-chip dummy MEMS bridge. A 3.2ms measurement results in
13bit resolution while consuming 35µA from a 1.5V supply occupying 0.148mm2. A comparison to
the State-of-the-Art proofs the converter concept to be competitive. However, a clear trend toward
hybrid solutions can be seen, which indicates to be superior in many aspects. O ering a concept
which could be combined with other converters proof to be beneficial in terms of overall e ciency.
A traditional first-order discrete-time modulator is a very common building block within converters.
Interestingly, a direct comparison shows many similarities to the proposed noise-shaping
Dual-Slope based concept. A high-level and circuit-level analysis is revealing, since it points out a
noise- versus sensor power-consumption trade-o between the two converter approaches. While the
concept is superior in terms of output resolution, the Dual-Slope converter is advantageous for
low-power medium-performance applications when large absolute sensor capacitors are present.
An inherent property of the proposed Dual-Slope based converter is the availability of the quantization
error in the analog domain. It is this fact which makes it easy to be used within a
Multi-stAge-noise-SHaping (MASH) architecture. This concept is proven within a 1-1 MASH example
on both system- and circuit-level where two Dual-Slope based converters are used. It is also
worth mentioning, that the second stage could be exchanged by any type of converter. However, a
mismatch analysis indicates commonly high matching requirements. Further adaptations towards
Sturdy-MASH (SMASH) architectures would be necessary to be more competitive.
Description
Mención Internacional en el título de doctor
Keywords
CMOS technology, Capacitance-to-Digital Converters (CDCs), Capacitive sensors, Switched-capacitors, Multi-stAge-noise-SHaping (MASH) architecture