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Error sensitivity study of FFT architectures implemented in FPGA

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Abstract
This work studies the impact that the architectural choices can have in the error mitigation of a digital processing module such as the Fast Fourier Transform. To this purpose, several serial and pipelined architectures were implemented in FPGA using Block Triple Modular Redundancy and analysed under a fault injection approach that was previously validated with radiation. These architectures were compared with respect to error rate, common mode failure rate and signal-to-noise ratio. Experimental results show that the error rate is strongly correlated with the use of resources when using a similar architecture. However, pipelined architectures tend to have more common mode failures but with lower signal-to-noise ratio than a serial architecture.
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Keywords
Triple modular redundancy, Fast fourier transform, SRAM-based FPGA, Common Mode Failures
Bibliographic citation
García-Astudillo, L., Lindoso, A., Entrena, L., Martín, H., & García-Valderas, M. (2021). Error sensitivity study of FFT architectures implemented in FPGA. Microelectronics Reliability, 126, 114298.