Publication:
A lightweight implementation of the Tav-128 hash function

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2017-06-10
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Institute of Electronics, Information and Communication Engineers
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Abstract
In this article we discuss the hardware implementation of a lightweight hash function, named Tav-128 [1], which was purposely designed for constrained devices such as low-cost RFID tags. In the original paper, the authors only provide an estimation of the hardware complexity. Motivated for this, we describe both an ASIC and an FPGA-based implementation of the aforementioned cryptographic primitive, and examine the performance of three architectures optimizing different criteria: area, throughput, and a trade-off between both of them.
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Hardware implementation, Hash function, ASIC, FPGA
Bibliographic citation
Martín, H., Peris-López, P., San Millán, E., & Tapiador, J. E. (2017). A lightweight implementation of the TAV-128 Hash function. IEICE Electronics Express, 14(11), 1-9.