Publication:
A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA

Loading...
Thumbnail Image
Identifiers
Publication date
2017-01
Defense date
Advisors
Tutors
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE
Impact
Google Scholar
Export
Research Projects
Organizational Units
Journal Issue
Abstract
In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and fault injection in an incremental manner. The error mitigation approach combines the use of SEC/DED codes for memories, a hardware monitor to detect control-flow errors, software-based techniques to detect data errors and configuration memory scrubbing with repair to avoid error accumulation. The proposed solution can significantly improve fault tolerance and can be fully embedded in a low-end FPGA, with reduced overhead and low intrusiveness.
Description
Keywords
Fault tolerance, Hybrid fault-tolerance techniques, Microprocessors, Neutron cross-section, SEEs, Soft errors
Bibliographic citation
Lindoso, A., Entrena, L., Garcia-Valderas, M. & Parra, L. (2017). A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA. IEEE Transactions on Nuclear Science, 64(1), pp. 374–381.