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BPR-TCAM--Block and partial reconfiguration based TCAM on Xilinx FPGAs

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2020-02-01
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MDPI
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Abstract
Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.
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TCAMs, Packet classification, FPGA, Partial reconfiguration
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Ullah, A., Zahir, A., Khan, N. A., Ahmad, W., Ramos, A., & Reviriego, P. (2020). BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs. Electronics, 9(2), 353.