Publication: PTM-based hybrid error-detection architecture for ARM microprocessors
dc.affiliation.dpto | UC3M. Departamento de Tecnología Electrónica | es |
dc.affiliation.grupoinv | UC3M. Grupo de Investigación: Diseño Microelectrónico y Aplicaciones (DMA) | es |
dc.contributor.author | Peña Frenandez, M. | |
dc.contributor.author | Lindoso Muñoz, Almudena | |
dc.contributor.author | Entrena Arrontes, Luis Alfonso | |
dc.contributor.author | García Valderas, Mario | |
dc.contributor.author | Philippe, S. | |
dc.contributor.author | Morilla, Y. | |
dc.contributor.author | Martin Holgado, P. | |
dc.contributor.funder | Ministerio de Economía y Competitividad (España) | es |
dc.contributor.funder | Comunidad de Madrid | es |
dc.date.accessioned | 2021-05-20T08:54:45Z | |
dc.date.available | 2021-05-20T08:54:45Z | |
dc.date.issued | 2018-09 | |
dc.description.abstract | This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS microprocessors because it does not modify the microprocessor architecture and is able to detect errors thanks to the reuse of its trace subsystem. Validation has been performed by proton irradiation and fault injection campaigns on a Zynq AP SoC including a Cortex-A9 ARM microprocessor and an implementation of the proposed hardware monitor in programmable logic. Experimental results demonstrate that a high error detection rate can be achieved on a commercial microprocessor. | en |
dc.format.extent | 6 | |
dc.identifier.bibliographicCitation | Peña-Fernandez, M., Lindoso, A., Entrena, L., Garcia-Valderas, M., Philippe, S., Morilla, Y. & Martin-Holgado, P. (2018). PTM-based hybrid error-detection architecture for ARM microprocessors. Microelectronics Reliability, vol. 88-90, pp. 925–930. | en |
dc.identifier.doi | https://doi.org/10.1016/j.microrel.2018.07.074 | |
dc.identifier.issn | 0026-2714 | |
dc.identifier.publicationfirstpage | 925 | |
dc.identifier.publicationlastpage | 930 | |
dc.identifier.publicationtitle | Microelectronics Reliability | en |
dc.identifier.publicationvolume | 88-90 | |
dc.identifier.uri | https://hdl.handle.net/10016/32694 | |
dc.identifier.uxxi | AR/0000022768 | |
dc.language.iso | eng | |
dc.publisher | Elsevier | en |
dc.relation.projectID | Gobierno de España. ESP2015-68245-C4-1-P | es |
dc.relation.projectID | Comunidad de Madrid. IND2017/TIC-7776 | es |
dc.rights | © 2018 Elsevier Ltd. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 España | * |
dc.rights.accessRights | open access | |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ | * |
dc.subject.eciencia | Electrónica | es |
dc.title | PTM-based hybrid error-detection architecture for ARM microprocessors | en |
dc.type | research article | * |
dc.type.hasVersion | AM | * |
dspace.entity.type | Publication |
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