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PTM-based hybrid error-detection architecture for ARM microprocessors

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dc.affiliation.dptoUC3M. Departamento de Tecnología Electrónicaes
dc.affiliation.grupoinvUC3M. Grupo de Investigación: Diseño Microelectrónico y Aplicaciones (DMA)es
dc.contributor.authorPeña Frenandez, M.
dc.contributor.authorLindoso Muñoz, Almudena
dc.contributor.authorEntrena Arrontes, Luis Alfonso
dc.contributor.authorGarcía Valderas, Mario
dc.contributor.authorPhilippe, S.
dc.contributor.authorMorilla, Y.
dc.contributor.authorMartin Holgado, P.
dc.contributor.funderMinisterio de Economía y Competitividad (España)es
dc.contributor.funderComunidad de Madrides
dc.date.accessioned2021-05-20T08:54:45Z
dc.date.available2021-05-20T08:54:45Z
dc.date.issued2018-09
dc.description.abstractThis work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS microprocessors because it does not modify the microprocessor architecture and is able to detect errors thanks to the reuse of its trace subsystem. Validation has been performed by proton irradiation and fault injection campaigns on a Zynq AP SoC including a Cortex-A9 ARM microprocessor and an implementation of the proposed hardware monitor in programmable logic. Experimental results demonstrate that a high error detection rate can be achieved on a commercial microprocessor.en
dc.format.extent6
dc.identifier.bibliographicCitationPeña-Fernandez, M., Lindoso, A., Entrena, L., Garcia-Valderas, M., Philippe, S., Morilla, Y. & Martin-Holgado, P. (2018). PTM-based hybrid error-detection architecture for ARM microprocessors. Microelectronics Reliability, vol. 88-90, pp. 925–930.en
dc.identifier.doihttps://doi.org/10.1016/j.microrel.2018.07.074
dc.identifier.issn0026-2714
dc.identifier.publicationfirstpage925
dc.identifier.publicationlastpage930
dc.identifier.publicationtitleMicroelectronics Reliabilityen
dc.identifier.publicationvolume88-90
dc.identifier.urihttps://hdl.handle.net/10016/32694
dc.identifier.uxxiAR/0000022768
dc.language.isoeng
dc.publisherElsevieren
dc.relation.projectIDGobierno de España. ESP2015-68245-C4-1-Pes
dc.relation.projectIDComunidad de Madrid. IND2017/TIC-7776es
dc.rights© 2018 Elsevier Ltd.
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights.accessRightsopen access
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.subject.ecienciaElectrónicaes
dc.titlePTM-based hybrid error-detection architecture for ARM microprocessorsen
dc.typeresearch article*
dc.type.hasVersionAM*
dspace.entity.typePublication
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